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ppc: Add fabs instruction to assembler

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Crementif 2025-11-23 16:52:47 +01:00
parent eb95e63d94
commit ad89b5ef37
2 changed files with 10 additions and 0 deletions
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9
src/Cemu/PPCAssembler/ppcAssembler.cpp
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@ -269,6 +269,7 @@ const char* ppcAssembler_getInstructionName(uint32 ppcAsmOp)
case PPCASM_OP_PS_NMSUB: return "PS_NMSUB";
case PPCASM_OP_FMR: return "FMR";
case PPCASM_OP_FABS: return "FABS";
case PPCASM_OP_FNEG: return "FNEG";
case PPCASM_OP_FRSP: return "FRSP";
case PPCASM_OP_FRSQRTE: return "FRSQRTE";
@ -1325,6 +1326,7 @@ PPCInstructionDef ppcInstructionTable[] =
{PPCASM_OP_FCMPO, 0, 63, 32|OPC_EXTENDED_BIT, OPC_NONE, OP_FORM_X_FP_CMP, FLG_DEFAULT, 0, 0, nullptr },
{PPCASM_OP_FNEG, 0, 63, 40|OPC_EXTENDED_BIT, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, { EncodedOperand_FPR(21), EncodedOperand_FPR(11) } },
{PPCASM_OP_FMR, 0, 63, 72|OPC_EXTENDED_BIT, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, { EncodedOperand_FPR(21), EncodedOperand_FPR(11) } },
{PPCASM_OP_FABS, 0, 63, 264|OPC_EXTENDED_BIT, OPC_NONE, OP_FORM_DYNAMIC, FLG_DEFAULT, 0, 0, nullptr, { EncodedOperand_FPR(21), EncodedOperand_FPR(11) } },
};
@ -3194,6 +3196,13 @@ void ppcAsmTestDisassembler()
checkOpFPR(0, 7);
checkOpFPR(1, 12);
// FABS
_testAsm(0xFC200A10, "fabs f1, f1");
disassemble(0xFC200A10, PPCASM_OP_FABS);
checkOperandMask(true, true);
checkOpFPR(0, 1);
checkOpFPR(1, 1);
// FCTIWZ
_testAsm(0xFD80401E, "fctiwz f12, f8");
disassemble(0xFD80401E, PPCASM_OP_FCTIWZ);

1
src/Cemu/PPCAssembler/ppcAssembler.h
View file

@ -233,6 +233,7 @@ enum PPCASM_OP
// FP
PPCASM_OP_FMR,
PPCASM_OP_FABS,
PPCASM_OP_FNEG,
PPCASM_OP_FRSP,
PPCASM_OP_FRSQRTE,