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PowerPC recompiler rework (#641)
This commit is contained in:
Exzap
GitHub
parent
06233e3462
commit
b089ae5b32
54 changed files with 15433 additions and 12397 deletions
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#include "../PPCRecompiler.h"
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#include "../PPCRecompilerIml.h"
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#include "IMLRegisterAllocatorRanges.h"
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#include "util/helpers/MemoryPool.h"
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uint32 IMLRA_GetNextIterationIndex();
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IMLRegID raLivenessRange::GetVirtualRegister() const
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{
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return virtualRegister;
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}
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sint32 raLivenessRange::GetPhysicalRegister() const
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{
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return physicalRegister;
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}
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IMLName raLivenessRange::GetName() const
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{
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return name;
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}
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void raLivenessRange::SetPhysicalRegister(IMLPhysReg physicalRegister)
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{
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this->physicalRegister = physicalRegister;
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}
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void raLivenessRange::SetPhysicalRegisterForCluster(IMLPhysReg physicalRegister)
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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for(auto& range : clusterRanges)
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range->physicalRegister = physicalRegister;
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}
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boost::container::small_vector<raLivenessRange*, 128> raLivenessRange::GetAllSubrangesInCluster()
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{
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uint32 iterationIndex = IMLRA_GetNextIterationIndex();
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boost::container::small_vector<raLivenessRange*, 128> subranges;
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subranges.push_back(this);
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this->lastIterationIndex = iterationIndex;
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size_t i = 0;
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while(i<subranges.size())
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{
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raLivenessRange* cur = subranges[i];
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i++;
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// check successors
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if(cur->subrangeBranchTaken && cur->subrangeBranchTaken->lastIterationIndex != iterationIndex)
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{
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cur->subrangeBranchTaken->lastIterationIndex = iterationIndex;
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subranges.push_back(cur->subrangeBranchTaken);
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}
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if(cur->subrangeBranchNotTaken && cur->subrangeBranchNotTaken->lastIterationIndex != iterationIndex)
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{
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cur->subrangeBranchNotTaken->lastIterationIndex = iterationIndex;
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subranges.push_back(cur->subrangeBranchNotTaken);
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}
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// check predecessors
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for(auto& prev : cur->previousRanges)
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{
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if(prev->lastIterationIndex != iterationIndex)
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{
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prev->lastIterationIndex = iterationIndex;
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subranges.push_back(prev);
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}
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}
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}
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return subranges;
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}
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void raLivenessRange::GetAllowedRegistersExRecursive(raLivenessRange* range, uint32 iterationIndex, IMLPhysRegisterSet& allowedRegs)
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{
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range->lastIterationIndex = iterationIndex;
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for (auto& it : range->list_fixedRegRequirements)
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allowedRegs &= it.allowedReg;
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// check successors
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if (range->subrangeBranchTaken && range->subrangeBranchTaken->lastIterationIndex != iterationIndex)
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GetAllowedRegistersExRecursive(range->subrangeBranchTaken, iterationIndex, allowedRegs);
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if (range->subrangeBranchNotTaken && range->subrangeBranchNotTaken->lastIterationIndex != iterationIndex)
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GetAllowedRegistersExRecursive(range->subrangeBranchNotTaken, iterationIndex, allowedRegs);
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// check predecessors
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for (auto& prev : range->previousRanges)
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{
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if (prev->lastIterationIndex != iterationIndex)
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GetAllowedRegistersExRecursive(prev, iterationIndex, allowedRegs);
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}
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};
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bool raLivenessRange::GetAllowedRegistersEx(IMLPhysRegisterSet& allowedRegisters)
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{
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uint32 iterationIndex = IMLRA_GetNextIterationIndex();
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allowedRegisters.SetAllAvailable();
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GetAllowedRegistersExRecursive(this, iterationIndex, allowedRegisters);
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return !allowedRegisters.HasAllAvailable();
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}
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IMLPhysRegisterSet raLivenessRange::GetAllowedRegisters(IMLPhysRegisterSet regPool)
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{
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IMLPhysRegisterSet fixedRegRequirements = regPool;
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if(interval.ExtendsPreviousSegment() || interval.ExtendsIntoNextSegment())
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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for(auto& subrange : clusterRanges)
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{
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for(auto& fixedRegLoc : subrange->list_fixedRegRequirements)
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fixedRegRequirements &= fixedRegLoc.allowedReg;
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}
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return fixedRegRequirements;
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}
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for(auto& fixedRegLoc : list_fixedRegRequirements)
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fixedRegRequirements &= fixedRegLoc.allowedReg;
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return fixedRegRequirements;
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}
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void PPCRecRARange_addLink_perVirtualGPR(std::unordered_map<IMLRegID, raLivenessRange*>& root, raLivenessRange* subrange)
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{
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IMLRegID regId = subrange->GetVirtualRegister();
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auto it = root.find(regId);
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if (it == root.end())
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{
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// new single element
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root.try_emplace(regId, subrange);
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subrange->link_sameVirtualRegister.prev = nullptr;
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subrange->link_sameVirtualRegister.next = nullptr;
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}
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else
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{
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// insert in first position
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raLivenessRange* priorFirst = it->second;
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subrange->link_sameVirtualRegister.next = priorFirst;
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it->second = subrange;
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subrange->link_sameVirtualRegister.prev = nullptr;
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priorFirst->link_sameVirtualRegister.prev = subrange;
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}
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}
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void PPCRecRARange_addLink_allSegmentRanges(raLivenessRange** root, raLivenessRange* subrange)
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{
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subrange->link_allSegmentRanges.next = *root;
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if (*root)
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(*root)->link_allSegmentRanges.prev = subrange;
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subrange->link_allSegmentRanges.prev = nullptr;
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*root = subrange;
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}
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void PPCRecRARange_removeLink_perVirtualGPR(std::unordered_map<IMLRegID, raLivenessRange*>& root, raLivenessRange* subrange)
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{
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#ifdef CEMU_DEBUG_ASSERT
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raLivenessRange* cur = root.find(subrange->GetVirtualRegister())->second;
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bool hasRangeFound = false;
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while(cur)
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{
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if(cur == subrange)
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{
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hasRangeFound = true;
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break;
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}
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cur = cur->link_sameVirtualRegister.next;
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}
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cemu_assert_debug(hasRangeFound);
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#endif
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IMLRegID regId = subrange->GetVirtualRegister();
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raLivenessRange* nextRange = subrange->link_sameVirtualRegister.next;
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raLivenessRange* prevRange = subrange->link_sameVirtualRegister.prev;
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raLivenessRange* newBase = prevRange ? prevRange : nextRange;
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if (prevRange)
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prevRange->link_sameVirtualRegister.next = subrange->link_sameVirtualRegister.next;
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if (nextRange)
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nextRange->link_sameVirtualRegister.prev = subrange->link_sameVirtualRegister.prev;
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if (!prevRange)
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{
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if (nextRange)
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{
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root.find(regId)->second = nextRange;
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}
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else
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{
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cemu_assert_debug(root.find(regId)->second == subrange);
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root.erase(regId);
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}
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}
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_sameVirtualRegister.prev = (raLivenessRange*)1;
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subrange->link_sameVirtualRegister.next = (raLivenessRange*)1;
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#endif
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}
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void PPCRecRARange_removeLink_allSegmentRanges(raLivenessRange** root, raLivenessRange* subrange)
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{
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raLivenessRange* tempPrev = subrange->link_allSegmentRanges.prev;
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if (subrange->link_allSegmentRanges.prev)
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subrange->link_allSegmentRanges.prev->link_allSegmentRanges.next = subrange->link_allSegmentRanges.next;
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else
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(*root) = subrange->link_allSegmentRanges.next;
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if (subrange->link_allSegmentRanges.next)
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subrange->link_allSegmentRanges.next->link_allSegmentRanges.prev = tempPrev;
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_allSegmentRanges.prev = (raLivenessRange*)1;
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subrange->link_allSegmentRanges.next = (raLivenessRange*)1;
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#endif
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}
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MemoryPoolPermanentObjects<raLivenessRange> memPool_livenessSubrange(4096);
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// startPosition and endPosition are inclusive
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raLivenessRange* IMLRA_CreateRange(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, IMLRegID virtualRegister, IMLName name, raInstructionEdge startPosition, raInstructionEdge endPosition)
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{
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raLivenessRange* range = memPool_livenessSubrange.acquireObj();
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range->previousRanges.clear();
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range->list_accessLocations.clear();
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range->list_fixedRegRequirements.clear();
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range->imlSegment = imlSegment;
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cemu_assert_debug(startPosition <= endPosition);
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range->interval.start = startPosition;
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range->interval.end = endPosition;
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// register mapping
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range->virtualRegister = virtualRegister;
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range->name = name;
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range->physicalRegister = -1;
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// default values
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range->hasStore = false;
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range->hasStoreDelayed = false;
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range->lastIterationIndex = 0;
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range->subrangeBranchNotTaken = nullptr;
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range->subrangeBranchTaken = nullptr;
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cemu_assert_debug(range->previousRanges.empty());
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range->_noLoad = false;
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// add to segment linked lists
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PPCRecRARange_addLink_perVirtualGPR(imlSegment->raInfo.linkedList_perVirtualRegister, range);
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PPCRecRARange_addLink_allSegmentRanges(&imlSegment->raInfo.linkedList_allSubranges, range);
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return range;
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}
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void _unlinkSubrange(raLivenessRange* range)
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{
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IMLSegment* imlSegment = range->imlSegment;
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PPCRecRARange_removeLink_perVirtualGPR(imlSegment->raInfo.linkedList_perVirtualRegister, range);
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PPCRecRARange_removeLink_allSegmentRanges(&imlSegment->raInfo.linkedList_allSubranges, range);
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// unlink reverse references
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if(range->subrangeBranchTaken)
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range->subrangeBranchTaken->previousRanges.erase(std::find(range->subrangeBranchTaken->previousRanges.begin(), range->subrangeBranchTaken->previousRanges.end(), range));
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if(range->subrangeBranchNotTaken)
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range->subrangeBranchNotTaken->previousRanges.erase(std::find(range->subrangeBranchNotTaken->previousRanges.begin(), range->subrangeBranchNotTaken->previousRanges.end(), range));
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range->subrangeBranchTaken = (raLivenessRange*)(uintptr_t)-1;
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range->subrangeBranchNotTaken = (raLivenessRange*)(uintptr_t)-1;
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// remove forward references
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for(auto& prev : range->previousRanges)
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{
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if(prev->subrangeBranchTaken == range)
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prev->subrangeBranchTaken = nullptr;
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if(prev->subrangeBranchNotTaken == range)
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prev->subrangeBranchNotTaken = nullptr;
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}
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range->previousRanges.clear();
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}
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void IMLRA_DeleteRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* range)
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{
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_unlinkSubrange(range);
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range->list_accessLocations.clear();
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range->list_fixedRegRequirements.clear();
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memPool_livenessSubrange.releaseObj(range);
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}
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void IMLRA_DeleteRangeCluster(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* range)
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{
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auto clusterRanges = range->GetAllSubrangesInCluster();
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for (auto& subrange : clusterRanges)
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IMLRA_DeleteRange(ppcImlGenContext, subrange);
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}
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void IMLRA_DeleteAllRanges(ppcImlGenContext_t* ppcImlGenContext)
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{
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for(auto& seg : ppcImlGenContext->segmentList2)
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{
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raLivenessRange* cur;
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while(cur = seg->raInfo.linkedList_allSubranges)
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IMLRA_DeleteRange(ppcImlGenContext, cur);
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seg->raInfo.linkedList_allSubranges = nullptr;
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seg->raInfo.linkedList_perVirtualRegister.clear();
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}
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}
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void IMLRA_MergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange, raLivenessRange* absorbedSubrange)
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{
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#ifdef CEMU_DEBUG_ASSERT
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PPCRecRA_debugValidateSubrange(subrange);
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PPCRecRA_debugValidateSubrange(absorbedSubrange);
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if (subrange->imlSegment != absorbedSubrange->imlSegment)
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assert_dbg();
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cemu_assert_debug(subrange->interval.end == absorbedSubrange->interval.start);
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if (subrange->subrangeBranchTaken || subrange->subrangeBranchNotTaken)
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assert_dbg();
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if (subrange == absorbedSubrange)
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assert_dbg();
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#endif
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// update references
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subrange->subrangeBranchTaken = absorbedSubrange->subrangeBranchTaken;
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subrange->subrangeBranchNotTaken = absorbedSubrange->subrangeBranchNotTaken;
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absorbedSubrange->subrangeBranchTaken = nullptr;
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absorbedSubrange->subrangeBranchNotTaken = nullptr;
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if(subrange->subrangeBranchTaken)
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*std::find(subrange->subrangeBranchTaken->previousRanges.begin(), subrange->subrangeBranchTaken->previousRanges.end(), absorbedSubrange) = subrange;
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if(subrange->subrangeBranchNotTaken)
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*std::find(subrange->subrangeBranchNotTaken->previousRanges.begin(), subrange->subrangeBranchNotTaken->previousRanges.end(), absorbedSubrange) = subrange;
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// merge usage locations
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for (auto& accessLoc : absorbedSubrange->list_accessLocations)
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subrange->list_accessLocations.push_back(accessLoc);
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absorbedSubrange->list_accessLocations.clear();
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// merge fixed reg locations
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#ifdef CEMU_DEBUG_ASSERT
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if(!subrange->list_fixedRegRequirements.empty() && !absorbedSubrange->list_fixedRegRequirements.empty())
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{
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cemu_assert_debug(subrange->list_fixedRegRequirements.back().pos < absorbedSubrange->list_fixedRegRequirements.front().pos);
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}
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#endif
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for (auto& fixedReg : absorbedSubrange->list_fixedRegRequirements)
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subrange->list_fixedRegRequirements.push_back(fixedReg);
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absorbedSubrange->list_fixedRegRequirements.clear();
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subrange->interval.end = absorbedSubrange->interval.end;
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PPCRecRA_debugValidateSubrange(subrange);
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IMLRA_DeleteRange(ppcImlGenContext, absorbedSubrange);
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}
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// remove all inter-segment connections from the range cluster and split it into local ranges. Ranges are trimmed and if they have no access location they will be removed
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void IMLRA_ExplodeRangeCluster(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* originRange)
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{
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cemu_assert_debug(originRange->interval.ExtendsPreviousSegment() || originRange->interval.ExtendsIntoNextSegment()); // only call this on ranges that span multiple segments
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auto clusterRanges = originRange->GetAllSubrangesInCluster();
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for (auto& subrange : clusterRanges)
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{
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if (subrange->list_accessLocations.empty())
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continue;
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raInterval interval;
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interval.SetInterval(subrange->list_accessLocations.front().pos, subrange->list_accessLocations.back().pos);
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raLivenessRange* newSubrange = IMLRA_CreateRange(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), interval.start, interval.end);
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// copy locations and fixed reg indices
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newSubrange->list_accessLocations = subrange->list_accessLocations;
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newSubrange->list_fixedRegRequirements = subrange->list_fixedRegRequirements;
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if(originRange->HasPhysicalRegister())
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{
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cemu_assert_debug(subrange->list_fixedRegRequirements.empty()); // avoid unassigning a register from a range with a fixed register requirement
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}
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// validate
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if(!newSubrange->list_accessLocations.empty())
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{
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cemu_assert_debug(newSubrange->list_accessLocations.front().pos >= newSubrange->interval.start);
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cemu_assert_debug(newSubrange->list_accessLocations.back().pos <= newSubrange->interval.end);
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}
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if(!newSubrange->list_fixedRegRequirements.empty())
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{
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cemu_assert_debug(newSubrange->list_fixedRegRequirements.front().pos >= newSubrange->interval.start); // fixed register requirements outside of the actual access range probably means there is a mistake in GetInstructionFixedRegisters()
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cemu_assert_debug(newSubrange->list_fixedRegRequirements.back().pos <= newSubrange->interval.end);
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}
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}
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// delete the original range cluster
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IMLRA_DeleteRangeCluster(ppcImlGenContext, originRange);
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}
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#ifdef CEMU_DEBUG_ASSERT
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void PPCRecRA_debugValidateSubrange(raLivenessRange* range)
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{
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// validate subrange
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if (range->subrangeBranchTaken && range->subrangeBranchTaken->imlSegment != range->imlSegment->nextSegmentBranchTaken)
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assert_dbg();
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if (range->subrangeBranchNotTaken && range->subrangeBranchNotTaken->imlSegment != range->imlSegment->nextSegmentBranchNotTaken)
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assert_dbg();
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if(range->subrangeBranchTaken || range->subrangeBranchNotTaken)
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{
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cemu_assert_debug(range->interval.end.ConnectsToNextSegment());
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}
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if(!range->previousRanges.empty())
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{
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cemu_assert_debug(range->interval.start.ConnectsToPreviousSegment());
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}
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// validate locations
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if (!range->list_accessLocations.empty())
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{
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cemu_assert_debug(range->list_accessLocations.front().pos >= range->interval.start);
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cemu_assert_debug(range->list_accessLocations.back().pos <= range->interval.end);
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}
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// validate fixed reg requirements
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if (!range->list_fixedRegRequirements.empty())
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{
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cemu_assert_debug(range->list_fixedRegRequirements.front().pos >= range->interval.start);
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cemu_assert_debug(range->list_fixedRegRequirements.back().pos <= range->interval.end);
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for(sint32 i = 0; i < (sint32)range->list_fixedRegRequirements.size()-1; i++)
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cemu_assert_debug(range->list_fixedRegRequirements[i].pos < range->list_fixedRegRequirements[i+1].pos);
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}
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}
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#else
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void PPCRecRA_debugValidateSubrange(raLivenessRange* range) {}
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#endif
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// trim start and end of range to match first and last read/write locations
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// does not trim start/endpoints which extend into the next/previous segment
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void IMLRA_TrimRangeToUse(raLivenessRange* range)
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{
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if(range->list_accessLocations.empty())
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{
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// special case where we trim ranges extending from other segments to a single instruction edge
|
||||
cemu_assert_debug(!range->interval.start.IsInstructionIndex() || !range->interval.end.IsInstructionIndex());
|
||||
if(range->interval.start.IsInstructionIndex())
|
||||
range->interval.start = range->interval.end;
|
||||
if(range->interval.end.IsInstructionIndex())
|
||||
range->interval.end = range->interval.start;
|
||||
return;
|
||||
}
|
||||
// trim start and end
|
||||
raInterval prevInterval = range->interval;
|
||||
if(range->interval.start.IsInstructionIndex())
|
||||
range->interval.start = range->list_accessLocations.front().pos;
|
||||
if(range->interval.end.IsInstructionIndex())
|
||||
range->interval.end = range->list_accessLocations.back().pos;
|
||||
// extra checks
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
cemu_assert_debug(range->interval.start <= range->interval.end);
|
||||
for(auto& loc : range->list_accessLocations)
|
||||
{
|
||||
cemu_assert_debug(range->interval.ContainsEdge(loc.pos));
|
||||
}
|
||||
cemu_assert_debug(prevInterval.ContainsWholeInterval(range->interval));
|
||||
#endif
|
||||
}
|
||||
|
||||
// split range at the given position
|
||||
// After the split there will be two ranges:
|
||||
// head -> subrange is shortened to end at splitIndex (exclusive)
|
||||
// tail -> a new subrange that ranges from splitIndex (inclusive) to the end of the original subrange
|
||||
// if head has a physical register assigned it will not carry over to tail
|
||||
// The return value is the tail range
|
||||
// If trimToUsage is true, the end of the head subrange and the start of the tail subrange will be shrunk to fit the read/write locations within. If there are no locations then the range will be deleted
|
||||
raLivenessRange* IMLRA_SplitRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange*& subrange, raInstructionEdge splitPosition, bool trimToUsage)
|
||||
{
|
||||
cemu_assert_debug(splitPosition.IsInstructionIndex());
|
||||
cemu_assert_debug(!subrange->interval.IsNextSegmentOnly() && !subrange->interval.IsPreviousSegmentOnly());
|
||||
cemu_assert_debug(subrange->interval.ContainsEdge(splitPosition));
|
||||
// determine new intervals
|
||||
raInterval headInterval, tailInterval;
|
||||
headInterval.SetInterval(subrange->interval.start, splitPosition-1);
|
||||
tailInterval.SetInterval(splitPosition, subrange->interval.end);
|
||||
cemu_assert_debug(headInterval.start <= headInterval.end);
|
||||
cemu_assert_debug(tailInterval.start <= tailInterval.end);
|
||||
// create tail
|
||||
raLivenessRange* tailSubrange = IMLRA_CreateRange(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), tailInterval.start, tailInterval.end);
|
||||
tailSubrange->SetPhysicalRegister(subrange->GetPhysicalRegister());
|
||||
// carry over branch targets and update reverse references
|
||||
tailSubrange->subrangeBranchTaken = subrange->subrangeBranchTaken;
|
||||
tailSubrange->subrangeBranchNotTaken = subrange->subrangeBranchNotTaken;
|
||||
subrange->subrangeBranchTaken = nullptr;
|
||||
subrange->subrangeBranchNotTaken = nullptr;
|
||||
if(tailSubrange->subrangeBranchTaken)
|
||||
*std::find(tailSubrange->subrangeBranchTaken->previousRanges.begin(), tailSubrange->subrangeBranchTaken->previousRanges.end(), subrange) = tailSubrange;
|
||||
if(tailSubrange->subrangeBranchNotTaken)
|
||||
*std::find(tailSubrange->subrangeBranchNotTaken->previousRanges.begin(), tailSubrange->subrangeBranchNotTaken->previousRanges.end(), subrange) = tailSubrange;
|
||||
// we assume that list_locations is ordered by instruction index and contains no duplicate indices, so lets check that here just in case
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
if(subrange->list_accessLocations.size() > 1)
|
||||
{
|
||||
for(size_t i=0; i<subrange->list_accessLocations.size()-1; i++)
|
||||
{
|
||||
cemu_assert_debug(subrange->list_accessLocations[i].pos < subrange->list_accessLocations[i+1].pos);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
// split locations
|
||||
auto it = std::lower_bound(
|
||||
subrange->list_accessLocations.begin(), subrange->list_accessLocations.end(), splitPosition,
|
||||
[](const raAccessLocation& accessLoc, raInstructionEdge value) { return accessLoc.pos < value; }
|
||||
);
|
||||
size_t originalCount = subrange->list_accessLocations.size();
|
||||
tailSubrange->list_accessLocations.insert(tailSubrange->list_accessLocations.end(), it, subrange->list_accessLocations.end());
|
||||
subrange->list_accessLocations.erase(it, subrange->list_accessLocations.end());
|
||||
cemu_assert_debug(subrange->list_accessLocations.empty() || subrange->list_accessLocations.back().pos < splitPosition);
|
||||
cemu_assert_debug(tailSubrange->list_accessLocations.empty() || tailSubrange->list_accessLocations.front().pos >= splitPosition);
|
||||
cemu_assert_debug(subrange->list_accessLocations.size() + tailSubrange->list_accessLocations.size() == originalCount);
|
||||
// split fixed reg requirements
|
||||
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
||||
{
|
||||
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
||||
if (tailInterval.ContainsEdge(fixedReg->pos))
|
||||
{
|
||||
tailSubrange->list_fixedRegRequirements.push_back(*fixedReg);
|
||||
}
|
||||
}
|
||||
// remove tail fixed reg requirements from head
|
||||
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
||||
{
|
||||
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
||||
if (!headInterval.ContainsEdge(fixedReg->pos))
|
||||
{
|
||||
subrange->list_fixedRegRequirements.resize(i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
// adjust intervals
|
||||
subrange->interval = headInterval;
|
||||
tailSubrange->interval = tailInterval;
|
||||
// trim to hole
|
||||
if(trimToUsage)
|
||||
{
|
||||
if(subrange->list_accessLocations.empty() && (subrange->interval.start.IsInstructionIndex() && subrange->interval.end.IsInstructionIndex()))
|
||||
{
|
||||
IMLRA_DeleteRange(ppcImlGenContext, subrange);
|
||||
subrange = nullptr;
|
||||
}
|
||||
else
|
||||
{
|
||||
IMLRA_TrimRangeToUse(subrange);
|
||||
}
|
||||
if(tailSubrange->list_accessLocations.empty() && (tailSubrange->interval.start.IsInstructionIndex() && tailSubrange->interval.end.IsInstructionIndex()))
|
||||
{
|
||||
IMLRA_DeleteRange(ppcImlGenContext, tailSubrange);
|
||||
tailSubrange = nullptr;
|
||||
}
|
||||
else
|
||||
{
|
||||
IMLRA_TrimRangeToUse(tailSubrange);
|
||||
}
|
||||
}
|
||||
// validation
|
||||
cemu_assert_debug(!subrange || subrange->interval.start <= subrange->interval.end);
|
||||
cemu_assert_debug(!tailSubrange || tailSubrange->interval.start <= tailSubrange->interval.end);
|
||||
cemu_assert_debug(!tailSubrange || tailSubrange->interval.start >= splitPosition);
|
||||
if (!trimToUsage)
|
||||
cemu_assert_debug(!tailSubrange || tailSubrange->interval.start == splitPosition);
|
||||
|
||||
if(subrange)
|
||||
PPCRecRA_debugValidateSubrange(subrange);
|
||||
if(tailSubrange)
|
||||
PPCRecRA_debugValidateSubrange(tailSubrange);
|
||||
return tailSubrange;
|
||||
}
|
||||
|
||||
sint32 IMLRA_GetSegmentReadWriteCost(IMLSegment* imlSegment)
|
||||
{
|
||||
sint32 v = imlSegment->loopDepth + 1;
|
||||
v *= 5;
|
||||
return v*v; // 25, 100, 225, 400
|
||||
}
|
||||
|
||||
// calculate additional cost of range that it would have after calling _ExplodeRange() on it
|
||||
sint32 IMLRA_CalculateAdditionalCostOfRangeExplode(raLivenessRange* subrange)
|
||||
{
|
||||
auto ranges = subrange->GetAllSubrangesInCluster();
|
||||
sint32 cost = 0;//-PPCRecRARange_estimateTotalCost(ranges);
|
||||
for (auto& subrange : ranges)
|
||||
{
|
||||
if (subrange->list_accessLocations.empty())
|
||||
continue; // this range would be deleted and thus has no cost
|
||||
sint32 segmentLoadStoreCost = IMLRA_GetSegmentReadWriteCost(subrange->imlSegment);
|
||||
bool hasAdditionalLoad = subrange->interval.ExtendsPreviousSegment();
|
||||
bool hasAdditionalStore = subrange->interval.ExtendsIntoNextSegment();
|
||||
if(hasAdditionalLoad && subrange->list_accessLocations.front().IsWrite()) // if written before read then a load isn't necessary
|
||||
{
|
||||
cemu_assert_debug(!subrange->list_accessLocations.front().IsRead());
|
||||
cost += segmentLoadStoreCost;
|
||||
}
|
||||
if(hasAdditionalStore)
|
||||
{
|
||||
bool hasWrite = std::find_if(subrange->list_accessLocations.begin(), subrange->list_accessLocations.end(), [](const raAccessLocation& loc) { return loc.IsWrite(); }) != subrange->list_accessLocations.end();
|
||||
if(!hasWrite) // ranges which don't modify their value do not need to be stored
|
||||
cost += segmentLoadStoreCost;
|
||||
}
|
||||
}
|
||||
// todo - properly calculating all the data-flow dependency based costs is more complex so this currently is an approximation
|
||||
return cost;
|
||||
}
|
||||
|
||||
sint32 IMLRA_CalculateAdditionalCostAfterSplit(raLivenessRange* subrange, raInstructionEdge splitPosition)
|
||||
{
|
||||
// validation
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
if (subrange->interval.ExtendsIntoNextSegment())
|
||||
assert_dbg();
|
||||
#endif
|
||||
cemu_assert_debug(splitPosition.IsInstructionIndex());
|
||||
|
||||
sint32 cost = 0;
|
||||
// find split position in location list
|
||||
if (subrange->list_accessLocations.empty())
|
||||
return 0;
|
||||
if (splitPosition <= subrange->list_accessLocations.front().pos)
|
||||
return 0;
|
||||
if (splitPosition > subrange->list_accessLocations.back().pos)
|
||||
return 0;
|
||||
|
||||
size_t firstTailLocationIndex = 0;
|
||||
for (size_t i = 0; i < subrange->list_accessLocations.size(); i++)
|
||||
{
|
||||
if (subrange->list_accessLocations[i].pos >= splitPosition)
|
||||
{
|
||||
firstTailLocationIndex = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
std::span<raAccessLocation> headLocations{subrange->list_accessLocations.data(), firstTailLocationIndex};
|
||||
std::span<raAccessLocation> tailLocations{subrange->list_accessLocations.data() + firstTailLocationIndex, subrange->list_accessLocations.size() - firstTailLocationIndex};
|
||||
cemu_assert_debug(headLocations.empty() || headLocations.back().pos < splitPosition);
|
||||
cemu_assert_debug(tailLocations.empty() || tailLocations.front().pos >= splitPosition);
|
||||
|
||||
sint32 segmentLoadStoreCost = IMLRA_GetSegmentReadWriteCost(subrange->imlSegment);
|
||||
|
||||
auto CalculateCostFromLocationRange = [segmentLoadStoreCost](std::span<raAccessLocation> locations, bool trackLoadCost = true, bool trackStoreCost = true) -> sint32
|
||||
{
|
||||
if(locations.empty())
|
||||
return 0;
|
||||
sint32 cost = 0;
|
||||
if(locations.front().IsRead() && trackLoadCost)
|
||||
cost += segmentLoadStoreCost; // not overwritten, so there is a load cost
|
||||
bool hasWrite = std::find_if(locations.begin(), locations.end(), [](const raAccessLocation& loc) { return loc.IsWrite(); }) != locations.end();
|
||||
if(hasWrite && trackStoreCost)
|
||||
cost += segmentLoadStoreCost; // modified, so there is a store cost
|
||||
return cost;
|
||||
};
|
||||
|
||||
sint32 baseCost = CalculateCostFromLocationRange(subrange->list_accessLocations);
|
||||
|
||||
bool tailOverwritesValue = !tailLocations.empty() && !tailLocations.front().IsRead() && tailLocations.front().IsWrite();
|
||||
|
||||
sint32 newCost = CalculateCostFromLocationRange(headLocations) + CalculateCostFromLocationRange(tailLocations, !tailOverwritesValue, true);
|
||||
cemu_assert_debug(newCost >= baseCost);
|
||||
cost = newCost - baseCost;
|
||||
|
||||
return cost;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue