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PPCRec: Rework floating point instructions (#1554)
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22 changed files with 1428 additions and 2879 deletions
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@ -126,46 +126,22 @@ enum
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PPCREC_IML_OP_SRW, // SRW (shift based on register by up to 63 bits)
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PPCREC_IML_OP_CNTLZW,
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// FPU
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PPCREC_IML_OP_FPR_ADD_BOTTOM,
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PPCREC_IML_OP_FPR_ADD_PAIR,
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PPCREC_IML_OP_FPR_SUB_PAIR,
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PPCREC_IML_OP_FPR_SUB_BOTTOM,
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PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM,
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PPCREC_IML_OP_FPR_MULTIPLY_PAIR,
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PPCREC_IML_OP_FPR_DIVIDE_BOTTOM,
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PPCREC_IML_OP_FPR_DIVIDE_PAIR,
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PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM_AND_TOP,
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PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM_AND_TOP,
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PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM,
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PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_TOP, // leave bottom of destination untouched
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PPCREC_IML_OP_FPR_COPY_TOP_TO_TOP, // leave bottom of destination untouched
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PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM, // leave top of destination untouched
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PPCREC_IML_OP_FPR_COPY_BOTTOM_AND_TOP_SWAPPED,
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PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64, // expand bottom f32 to f64 in bottom and top half
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PPCREC_IML_OP_FPR_FCMPO_BOTTOM, // deprecated
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PPCREC_IML_OP_FPR_FCMPU_BOTTOM, // deprecated
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PPCREC_IML_OP_FPR_FCMPU_TOP, // deprecated
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PPCREC_IML_OP_FPR_NEGATE_BOTTOM,
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PPCREC_IML_OP_FPR_NEGATE_PAIR,
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PPCREC_IML_OP_FPR_ABS_BOTTOM, // abs(fp0)
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PPCREC_IML_OP_FPR_ABS_PAIR,
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PPCREC_IML_OP_FPR_FRES_PAIR, // 1.0/fp approx (Espresso accuracy)
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PPCREC_IML_OP_FPR_FRSQRTE_PAIR, // 1.0/sqrt(fp) approx (Espresso accuracy)
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PPCREC_IML_OP_FPR_NEGATIVE_ABS_BOTTOM, // -abs(fp0)
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PPCREC_IML_OP_FPR_ASSIGN,
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PPCREC_IML_OP_FPR_LOAD_ONE, // load constant 1.0 into register
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PPCREC_IML_OP_FPR_ADD,
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PPCREC_IML_OP_FPR_SUB,
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PPCREC_IML_OP_FPR_MULTIPLY,
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PPCREC_IML_OP_FPR_DIVIDE,
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PPCREC_IML_OP_FPR_EXPAND_F32_TO_F64, // expand f32 to f64 in-place
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PPCREC_IML_OP_FPR_NEGATE,
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PPCREC_IML_OP_FPR_ABS, // abs(fpr)
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PPCREC_IML_OP_FPR_NEGATIVE_ABS, // -abs(fpr)
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PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_BOTTOM, // round 64bit double to 64bit double with 32bit float precision (in bottom half of xmm register)
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PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_PAIR, // round two 64bit doubles to 64bit double with 32bit float precision
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PPCREC_IML_OP_FPR_BOTTOM_RECIPROCAL_SQRT,
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PPCREC_IML_OP_FPR_BOTTOM_FCTIWZ,
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PPCREC_IML_OP_FPR_SELECT_BOTTOM, // selectively copy bottom value from operand B or C based on value in operand A
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PPCREC_IML_OP_FPR_SELECT_PAIR, // selectively copy top/bottom from operand B or C based on value in top/bottom of operand A
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// PS
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PPCREC_IML_OP_FPR_SUM0,
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PPCREC_IML_OP_FPR_SUM1,
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// R_R_R only
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// R_R_S32 only
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PPCREC_IML_OP_FPR_FCTIWZ,
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PPCREC_IML_OP_FPR_SELECT, // selectively copy bottom value from operand B or C based on value in operand A
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// Conversion (FPR_R_R)
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PPCREC_IML_OP_FPR_INT_TO_FLOAT, // convert integer value in gpr to floating point value in fpr
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PPCREC_IML_OP_FPR_FLOAT_TO_INT, // convert floating point value in fpr to integer value in gpr
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// R_R_R + R_R_S32
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PPCREC_IML_OP_ADD, // also R_R_R_CARRY
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@ -275,7 +251,7 @@ enum // IMLName
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PPCREC_NAME_TEMPORARY = 1000,
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PPCREC_NAME_R0 = 2000,
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PPCREC_NAME_SPR0 = 3000,
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PPCREC_NAME_FPR0 = 4000,
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PPCREC_NAME_FPR_HALF = 4800, // Counts PS0 and PS1 separately. E.g. fp3.ps1 is at offset 3 * 2 + 1
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PPCREC_NAME_TEMPORARY_FPR0 = 5000, // 0 to 7
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PPCREC_NAME_XER_CA = 6000, // carry bit from XER
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PPCREC_NAME_XER_OV = 6001, // overflow bit from XER
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@ -291,39 +267,14 @@ enum // IMLName
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enum
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{
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// fpr load
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PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0,
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PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1,
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PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0,
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PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0,
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PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0,
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PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_S16_PS0,
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PPCREC_FPR_LD_MODE_PSQ_S16_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_U16_PS0,
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PPCREC_FPR_LD_MODE_PSQ_U16_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_S8_PS0,
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PPCREC_FPR_LD_MODE_PSQ_S8_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_U8_PS0,
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PPCREC_FPR_LD_MODE_PSQ_U8_PS0_PS1,
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PPCREC_FPR_LD_MODE_SINGLE,
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PPCREC_FPR_LD_MODE_DOUBLE,
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// fpr store
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PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0, // store 1 single precision float from ps0
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PPCREC_FPR_ST_MODE_DOUBLE_FROM_PS0, // store 1 double precision float from ps0
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PPCREC_FPR_ST_MODE_SINGLE,
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PPCREC_FPR_ST_MODE_DOUBLE,
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PPCREC_FPR_ST_MODE_UI32_FROM_PS0, // store raw low-32bit of PS0
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PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0,
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PPCREC_FPR_ST_MODE_PSQ_FLOAT_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_FLOAT_PS0,
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PPCREC_FPR_ST_MODE_PSQ_S8_PS0,
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PPCREC_FPR_ST_MODE_PSQ_S8_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_U8_PS0,
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PPCREC_FPR_ST_MODE_PSQ_U8_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_U16_PS0,
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PPCREC_FPR_ST_MODE_PSQ_U16_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_S16_PS0,
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PPCREC_FPR_ST_MODE_PSQ_S16_PS0_PS1,
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};
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struct IMLUsedRegisters
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@ -463,7 +414,6 @@ struct IMLInstruction
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IMLReg registerData;
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IMLReg registerMem;
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IMLReg registerMem2;
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IMLReg registerGQR;
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uint8 copyWidth;
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struct
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{
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@ -471,7 +421,7 @@ struct IMLInstruction
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bool signExtend : 1;
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bool notExpanded : 1; // for floats
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}flags2;
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uint8 mode; // transfer mode (copy width, ps0/ps1 behavior)
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uint8 mode; // transfer mode
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sint32 immS32;
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}op_storeLoad;
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struct
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@ -752,6 +702,56 @@ struct IMLInstruction
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this->op_call_imm.regReturn = regReturn;
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}
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// FPR
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// load from memory
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void make_fpr_r_memory(IMLReg registerDestination, IMLReg registerMemory, sint32 immS32, uint32 mode, bool switchEndian)
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{
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this->type = PPCREC_IML_TYPE_FPR_LOAD;
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this->operation = 0;
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this->op_storeLoad.registerData = registerDestination;
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this->op_storeLoad.registerMem = registerMemory;
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this->op_storeLoad.immS32 = immS32;
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this->op_storeLoad.mode = mode;
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this->op_storeLoad.flags2.swapEndian = switchEndian;
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}
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void make_fpr_r_memory_indexed(IMLReg registerDestination, IMLReg registerMemory1, IMLReg registerMemory2, uint32 mode, bool switchEndian)
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{
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this->type = PPCREC_IML_TYPE_FPR_LOAD_INDEXED;
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this->operation = 0;
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this->op_storeLoad.registerData = registerDestination;
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this->op_storeLoad.registerMem = registerMemory1;
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this->op_storeLoad.registerMem2 = registerMemory2;
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this->op_storeLoad.immS32 = 0;
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this->op_storeLoad.mode = mode;
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this->op_storeLoad.flags2.swapEndian = switchEndian;
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}
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// store to memory
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void make_fpr_memory_r(IMLReg registerSource, IMLReg registerMemory, sint32 immS32, uint32 mode, bool switchEndian)
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{
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this->type = PPCREC_IML_TYPE_FPR_STORE;
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this->operation = 0;
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this->op_storeLoad.registerData = registerSource;
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this->op_storeLoad.registerMem = registerMemory;
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this->op_storeLoad.immS32 = immS32;
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this->op_storeLoad.mode = mode;
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this->op_storeLoad.flags2.swapEndian = switchEndian;
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}
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void make_fpr_memory_r_indexed(IMLReg registerSource, IMLReg registerMemory1, IMLReg registerMemory2, sint32 immS32, uint32 mode, bool switchEndian)
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{
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this->type = PPCREC_IML_TYPE_FPR_STORE_INDEXED;
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this->operation = 0;
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this->op_storeLoad.registerData = registerSource;
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this->op_storeLoad.registerMem = registerMemory1;
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this->op_storeLoad.registerMem2 = registerMemory2;
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this->op_storeLoad.immS32 = immS32;
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this->op_storeLoad.mode = mode;
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this->op_storeLoad.flags2.swapEndian = switchEndian;
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}
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void make_fpr_compare(IMLReg regA, IMLReg regB, IMLReg regR, IMLCondition cond)
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{
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this->type = PPCREC_IML_TYPE_FPR_COMPARE;
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@ -762,6 +762,44 @@ struct IMLInstruction
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this->op_fpr_compare.cond = cond;
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}
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void make_fpr_r(sint32 operation, IMLReg registerResult)
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{
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// OP (fpr)
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this->type = PPCREC_IML_TYPE_FPR_R;
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this->operation = operation;
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this->op_fpr_r.regR = registerResult;
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}
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void make_fpr_r_r(sint32 operation, IMLReg registerResult, IMLReg registerOperand, sint32 crRegister=PPC_REC_INVALID_REGISTER)
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{
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// fpr OP fpr
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this->type = PPCREC_IML_TYPE_FPR_R_R;
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this->operation = operation;
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this->op_fpr_r_r.regR = registerResult;
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this->op_fpr_r_r.regA = registerOperand;
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}
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void make_fpr_r_r_r(sint32 operation, IMLReg registerResult, IMLReg registerOperand1, IMLReg registerOperand2, sint32 crRegister=PPC_REC_INVALID_REGISTER)
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{
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// fpr = OP (fpr,fpr)
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this->type = PPCREC_IML_TYPE_FPR_R_R_R;
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this->operation = operation;
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this->op_fpr_r_r_r.regR = registerResult;
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this->op_fpr_r_r_r.regA = registerOperand1;
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this->op_fpr_r_r_r.regB = registerOperand2;
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}
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void make_fpr_r_r_r_r(sint32 operation, IMLReg registerResult, IMLReg registerOperandA, IMLReg registerOperandB, IMLReg registerOperandC, sint32 crRegister=PPC_REC_INVALID_REGISTER)
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{
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// fpr = OP (fpr,fpr,fpr)
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this->type = PPCREC_IML_TYPE_FPR_R_R_R_R;
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this->operation = operation;
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this->op_fpr_r_r_r_r.regR = registerResult;
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this->op_fpr_r_r_r_r.regA = registerOperandA;
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this->op_fpr_r_r_r_r.regB = registerOperandB;
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this->op_fpr_r_r_r_r.regC = registerOperandC;
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}
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/* X86 specific */
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void make_x86_eflags_jcc(IMLCondition cond, bool invertedCondition)
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{
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