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android: Update build system and optimize ARM NCE implementation
- Update Kotlin from 1.9.20 to 2.1.20-RC2 - Upgrade Java version from 17 to 21 - Update Android Gradle plugin from 8.1.2 to 8.9.0 - Update Gradle wrapper from 8.10.2 to 8.11.1 - Update NDK version to 29.0.13113456 rc1 - Update all Android dependencies to latest versions - Simplify ARM NCE implementation by removing custom TLB handling - Improve alignment and access fault handling - Update hardware BASE_CLOCK_RATE from 1.02GHz to 1.785GHz - Add citron Emulator Project copyright notices Signed-off-by: Zephyron <zephyron@citron-emu.org>
This commit is contained in:
Zephyron
parent
834cc89548
commit
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8 changed files with 57 additions and 192 deletions
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@ -1,5 +1,4 @@
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// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <cinttypes>
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@ -144,55 +143,30 @@ bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info,
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auto* fpctx = GetFloatingPointState(host_ctx);
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auto& memory = guest_ctx->system->ApplicationMemory();
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// Log the alignment fault for debugging
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LOG_DEBUG(Core_ARM, "Alignment fault at PC={:X}", host_ctx.pc);
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// Try to handle the instruction
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// Match and execute an instruction.
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auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx, fpctx);
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if (next_pc) {
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host_ctx.pc = *next_pc;
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return true;
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}
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// If we couldn't handle it, try to skip the instruction as a fallback
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LOG_DEBUG(Core_ARM, "Could not handle alignment fault, skipping instruction");
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host_ctx.pc += 4; // Skip to next instruction
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// Return true to continue execution
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return true;
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// We couldn't handle the access.
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return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
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}
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bool ArmNce::HandleGuestAccessFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
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auto* info = static_cast<siginfo_t*>(raw_info);
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const u64 fault_addr = reinterpret_cast<u64>(info->si_addr);
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auto& memory = guest_ctx->system->ApplicationMemory();
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// Get the ArmNce instance from the guest context
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ArmNce* nce = guest_ctx->parent;
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// Check TLB first
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if (TlbEntry* entry = nce->FindTlbEntry(fault_addr)) {
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if (!entry->writable && info->si_code == SEGV_ACCERR) {
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LOG_DEBUG(Core_ARM, "Write to read-only memory at {:X}", fault_addr);
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return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
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}
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// Try to handle an invalid access.
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// TODO: handle accesses which split a page?
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const Common::ProcessAddress addr =
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(reinterpret_cast<u64>(info->si_addr) & ~Memory::CITRON_PAGEMASK);
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if (guest_ctx->system->ApplicationMemory().InvalidateNCE(addr, Memory::CITRON_PAGESIZE)) {
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// We handled the access successfully and are returning to guest code.
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return true;
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}
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// TLB miss handling with better error checking
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if (memory.InvalidateNCE(fault_addr, Memory::CITRON_PAGESIZE)) {
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const u64 host_addr = reinterpret_cast<u64>(memory.GetPointer(fault_addr));
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if (host_addr) {
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nce->AddTlbEntry(fault_addr, host_addr, Memory::CITRON_PAGESIZE, true);
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return true;
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} else {
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LOG_DEBUG(Core_ARM, "Failed to get host address for guest address {:X}", fault_addr);
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}
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} else {
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LOG_DEBUG(Core_ARM, "Memory invalidation failed for address {:X}", fault_addr);
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}
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// We couldn't handle the access.
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return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
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}
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@ -403,81 +377,4 @@ void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
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this->ClearInstructionCache();
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}
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TlbEntry* ArmNce::FindTlbEntry(u64 guest_addr) {
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std::lock_guard lock(m_tlb_mutex);
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// Simple linear search - more reliable than complex indexing
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for (size_t i = 0; i < TLB_SIZE; i++) {
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TlbEntry& entry = m_tlb[i];
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if (entry.valid &&
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guest_addr >= entry.guest_addr &&
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guest_addr < (entry.guest_addr + entry.size)) {
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// Simple access tracking - just increment counter
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if (entry.access_count < 1000) { // Prevent overflow
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entry.access_count++;
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}
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return &entry;
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}
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}
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return nullptr;
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}
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void ArmNce::AddTlbEntry(u64 guest_addr, u64 host_addr, u32 size, bool writable) {
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// Validate addresses before proceeding
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if (!host_addr) {
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LOG_ERROR(Core_ARM, "Invalid host address for guest address {:X}", guest_addr);
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return;
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}
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std::lock_guard lock(m_tlb_mutex);
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// First try to find an invalid entry
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size_t replace_idx = TLB_SIZE;
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for (size_t i = 0; i < TLB_SIZE; i++) {
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if (!m_tlb[i].valid) {
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replace_idx = i;
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break;
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}
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}
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// If no invalid entries, use simple LRU
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if (replace_idx == TLB_SIZE) {
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u32 lowest_count = UINT32_MAX;
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for (size_t i = 0; i < TLB_SIZE; i++) {
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if (m_tlb[i].access_count < lowest_count) {
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lowest_count = m_tlb[i].access_count;
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replace_idx = i;
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}
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}
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}
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// Safety check
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if (replace_idx >= TLB_SIZE) {
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replace_idx = 0; // Fallback to first entry if something went wrong
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}
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// Page align the addresses for consistency
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const u64 page_mask = size - 1;
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const u64 aligned_guest = guest_addr & ~page_mask;
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const u64 aligned_host = host_addr & ~page_mask;
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m_tlb[replace_idx] = {
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.guest_addr = aligned_guest,
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.host_addr = aligned_host,
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.size = size,
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.valid = true,
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.writable = writable,
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.last_access_time = 0, // Not used in simplified implementation
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.access_count = 1
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};
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}
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void ArmNce::InvalidateTlb() {
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std::lock_guard lock(m_tlb_mutex);
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for (auto& entry : m_tlb) {
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entry.valid = false;
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}
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}
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} // namespace Core
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@ -1,11 +1,9 @@
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// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <mutex>
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#include <array>
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#include "core/arm/arm_interface.h"
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#include "core/arm/nce/guest_context.h"
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@ -18,21 +16,6 @@ namespace Core {
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class System;
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struct TlbEntry {
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u64 guest_addr;
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u64 host_addr;
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u32 size;
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bool valid;
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bool writable;
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u64 last_access_time; // For LRU tracking
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u32 access_count; // For access frequency tracking
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};
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// Improved TLB configuration
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constexpr size_t TLB_SETS = 64; // Number of sets
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constexpr size_t TLB_WAYS = 8; // Ways per set
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constexpr size_t TLB_SIZE = TLB_SETS * TLB_WAYS;
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class ArmNce final : public ArmInterface {
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public:
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ArmNce(System& system, bool uses_wall_clock, std::size_t core_index);
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@ -107,24 +90,6 @@ public:
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// Stack for signal processing.
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std::unique_ptr<u8[]> m_stack{};
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// Enhanced TLB implementation
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std::array<TlbEntry, TLB_SIZE> m_tlb{};
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std::mutex m_tlb_mutex;
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u64 m_tlb_access_counter{0};
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// TLB helper functions
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TlbEntry* FindTlbEntry(u64 guest_addr);
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void AddTlbEntry(u64 guest_addr, u64 host_addr, u32 size, bool writable);
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void InvalidateTlb();
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size_t GetTlbSetIndex(u64 guest_addr) const;
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size_t FindReplacementEntry(size_t set_start);
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void UpdateTlbEntryStats(TlbEntry& entry);
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// Thread context caching
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std::mutex m_context_mutex;
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Kernel::KThread* m_last_thread{nullptr};
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GuestContext m_cached_ctx{};
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};
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} // namespace Core
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@ -1,4 +1,5 @@
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// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
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// SPDX-FileCopyrightText: Copyright 2025 citron Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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@ -13,7 +14,7 @@ namespace Core {
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namespace Hardware {
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constexpr u64 BASE_CLOCK_RATE = 1'020'000'000; // Default CPU Frequency = 1020 MHz
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constexpr u64 BASE_CLOCK_RATE = 1'785'000'000; // Default CPU Frequency = 1785 MHz
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constexpr u64 CNTFREQ = 19'200'000; // CNTPCT_EL0 Frequency = 19.2 MHz
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constexpr u32 NUM_CPU_CORES = 4; // Number of CPU Cores
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