Vulkan: Revise feedback loop restriction to RDNA 3 GPUs

* Use RegEx to define RDNA 3 GPU name pattern

* Add device IDs for ROG Ally (X), since these are RDNA 3 devices
This commit is contained in:
KeatonTheBot 2025-04-30 23:13:59 -05:00
parent cb37aea614
commit e02463d779
3 changed files with 10 additions and 2 deletions

View file

@ -1525,8 +1525,8 @@ namespace Ryujinx.Graphics.Vulkan
private bool ChangeFeedbackLoop(FeedbackLoopAspects aspects)
{
// AMD Radeon RX GPUs + Qualcomm SoCs only
if ((Gd.Vendor == Vendor.Amd && Gd.GpuRenderer.Contains("RX")) || Gd.Vendor == Vendor.Qualcomm)
// AMD RDNA 3 GPUs + Qualcomm SoCs only
if (Gd.IsAmdRdna3 || Gd.Vendor == Vendor.Qualcomm)
{
if (_feedbackLoop != aspects)
{

View file

@ -21,6 +21,9 @@ namespace Ryujinx.Graphics.Vulkan
[GeneratedRegex("Radeon (((HD|R(5|7|9|X)) )?((M?[2-6]\\d{2}(\\D|$))|([7-8]\\d{3}(\\D|$))|Fury|Nano))|(Pro Duo)")]
public static partial Regex AmdGcnRegex();
[GeneratedRegex("Radeon ([7-8](\\d{2}\\d?)[MS]|PRO [VW]7(\\d{2}\\d?)|RX 7\\d{3}([MS]?| XTX?| GRE)?)")]
public static partial Regex AmdRdna3Regex();
[GeneratedRegex("NVIDIA GeForce (R|G)?TX? (\\d{3}\\d?)M?")]
public static partial Regex NvidiaConsumerClassRegex();

View file

@ -89,6 +89,7 @@ namespace Ryujinx.Graphics.Vulkan
internal bool IsAmdWindows { get; private set; }
internal bool IsIntelWindows { get; private set; }
internal bool IsAmdGcn { get; private set; }
internal bool IsAmdRdna3 { get; private set; }
internal bool IsNvidiaPreTuring { get; private set; }
internal bool IsIntelArc { get; private set; }
internal bool IsQualcommProprietary { get; private set; }
@ -373,6 +374,10 @@ namespace Ryujinx.Graphics.Vulkan
IsAmdGcn = !IsMoltenVk && Vendor == Vendor.Amd && VendorUtils.AmdGcnRegex().IsMatch(GpuRenderer);
IsAmdRdna3 = Vendor == Vendor.Amd && (VendorUtils.AmdRdna3Regex().IsMatch(GpuRenderer)
// ROG Ally (X) Device IDs
|| properties.DeviceID is 0x15BF or 0x15C8);
if (Vendor == Vendor.Nvidia)
{
var match = VendorUtils.NvidiaConsumerClassRegex().Match(GpuRenderer);