mirror of
https://git.ryujinx.app/kenji-nx/ryujinx.git
synced 2025-12-17 16:37:04 +00:00
[Ryujinx.Tests] Address dotnet-format issues (#5389)
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Fix new dotnet-format issues after rebase * Address review comments * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Format if-blocks correctly * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Apply suggestions from code review Co-authored-by: Ac_K <Acoustik666@gmail.com> * First dotnet format pass * Fix naming rule violations * Remove naming rule violation exceptions * Fix comment style * Use targeted new * Remove redundant code * Remove comment alignment * Remove naming rule exceptions * Add trailing commas * Use nameof expression * Reformat to add remaining trailing commas --------- Co-authored-by: Ac_K <Acoustik666@gmail.com>
This commit is contained in:
TSRBerry
GitHub
parent
6e28a4dd13
commit
e9848339dd
62 changed files with 2263 additions and 1929 deletions
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@ -14,13 +14,15 @@ namespace Ryujinx.Tests.Cpu
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public class CpuTest
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{
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protected static readonly ulong Size = MemoryBlock.GetPageSize();
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#pragma warning disable CA2211 // Non-constant fields should not be visible
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protected static ulong CodeBaseAddress = Size;
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protected static ulong DataBaseAddress = CodeBaseAddress + Size;
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#pragma warning restore CA2211
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private static bool Ignore_FpcrFz = false;
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private static bool Ignore_FpcrDn = false;
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private static readonly bool _ignoreFpcrFz = false;
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private static readonly bool _ignoreFpcrDn = false;
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private static bool IgnoreAllExcept_FpsrQc = false;
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private static readonly bool _ignoreAllExceptFpsrQc = false;
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private ulong _currAddress;
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@ -84,8 +86,8 @@ namespace Ryujinx.Tests.Cpu
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_context.Dispose();
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_ram.Dispose();
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_memory = null;
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_context = null;
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_memory = null;
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_context = null;
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_cpuContext = null;
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_unicornEmu = null;
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@ -109,38 +111,38 @@ namespace Ryujinx.Tests.Cpu
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protected ExecutionContext GetContext() => _context;
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protected void SetContext(ulong x0 = 0,
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ulong x1 = 0,
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ulong x2 = 0,
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ulong x3 = 0,
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ulong x31 = 0,
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V128 v0 = default,
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V128 v1 = default,
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V128 v2 = default,
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V128 v3 = default,
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V128 v4 = default,
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V128 v5 = default,
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V128 v30 = default,
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V128 v31 = default,
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpcr = 0,
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int fpsr = 0)
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protected void SetContext(ulong x0 = 0,
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ulong x1 = 0,
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ulong x2 = 0,
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ulong x3 = 0,
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ulong x31 = 0,
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V128 v0 = default,
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V128 v1 = default,
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V128 v2 = default,
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V128 v3 = default,
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V128 v4 = default,
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V128 v5 = default,
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V128 v30 = default,
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V128 v31 = default,
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpcr = 0,
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int fpsr = 0)
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{
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_context.SetX(0, x0);
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_context.SetX(1, x1);
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_context.SetX(2, x2);
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_context.SetX(3, x3);
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_context.SetX(0, x0);
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_context.SetX(1, x1);
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_context.SetX(2, x2);
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_context.SetX(3, x3);
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_context.SetX(31, x31);
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_context.SetV(0, v0);
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_context.SetV(1, v1);
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_context.SetV(2, v2);
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_context.SetV(3, v3);
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_context.SetV(4, v4);
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_context.SetV(5, v5);
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_context.SetV(0, v0);
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_context.SetV(1, v1);
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_context.SetV(2, v2);
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_context.SetV(3, v3);
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_context.SetV(4, v4);
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_context.SetV(5, v5);
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_context.SetV(30, v30);
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_context.SetV(31, v31);
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@ -156,20 +158,20 @@ namespace Ryujinx.Tests.Cpu
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_unicornEmu.X[1] = x1;
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_unicornEmu.X[2] = x2;
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_unicornEmu.X[3] = x3;
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_unicornEmu.SP = x31;
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_unicornEmu.SP = x31;
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[30] = V128ToSimdValue(v30);
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_unicornEmu.Q[31] = V128ToSimdValue(v31);
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.NegativeFlag = negative;
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_unicornEmu.Fpcr = fpcr;
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@ -186,34 +188,34 @@ namespace Ryujinx.Tests.Cpu
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}
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}
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protected ExecutionContext SingleOpcode(uint opcode,
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ulong x0 = 0,
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ulong x1 = 0,
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ulong x2 = 0,
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ulong x3 = 0,
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ulong x31 = 0,
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V128 v0 = default,
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V128 v1 = default,
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V128 v2 = default,
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V128 v3 = default,
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V128 v4 = default,
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V128 v5 = default,
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V128 v30 = default,
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V128 v31 = default,
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpcr = 0,
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int fpsr = 0,
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bool runUnicorn = true)
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protected ExecutionContext SingleOpcode(uint opcode,
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ulong x0 = 0,
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ulong x1 = 0,
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ulong x2 = 0,
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ulong x3 = 0,
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ulong x31 = 0,
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V128 v0 = default,
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V128 v1 = default,
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V128 v2 = default,
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V128 v3 = default,
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V128 v4 = default,
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V128 v5 = default,
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V128 v30 = default,
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V128 v31 = default,
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bool overflow = false,
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bool carry = false,
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bool zero = false,
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bool negative = false,
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int fpcr = 0,
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int fpsr = 0,
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bool runUnicorn = true)
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{
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if (Ignore_FpcrFz)
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if (_ignoreFpcrFz)
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{
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fpcr &= ~(1 << (int)Fpcr.Fz);
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}
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if (Ignore_FpcrDn)
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if (_ignoreFpcrDn)
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{
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fpcr &= ~(1 << (int)Fpcr.Dn);
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}
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@ -254,8 +256,8 @@ namespace Ryujinx.Tests.Cpu
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/// <summary>Round towards Minus Infinity mode.</summary>
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Rm,
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/// <summary>Round towards Zero mode.</summary>
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Rz
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};
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Rz,
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}
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/// <summary>Floating-point Control Register.</summary>
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protected enum Fpcr
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@ -263,15 +265,16 @@ namespace Ryujinx.Tests.Cpu
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/// <summary>Rounding Mode control field.</summary>
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RMode = 22,
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/// <summary>Flush-to-zero mode control bit.</summary>
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Fz = 24,
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Fz = 24,
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/// <summary>Default NaN mode control bit.</summary>
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Dn = 25,
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Dn = 25,
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/// <summary>Alternative half-precision control bit.</summary>
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Ahp = 26
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Ahp = 26,
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}
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/// <summary>Floating-point Status Register.</summary>
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[Flags] protected enum Fpsr
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[Flags]
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protected enum Fpsr
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{
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None = 0,
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@ -289,10 +292,11 @@ namespace Ryujinx.Tests.Cpu
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Idc = 1 << 7,
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/// <summary>Cumulative saturation bit.</summary>
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Qc = 1 << 27
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Qc = 1 << 27,
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}
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[Flags] protected enum FpSkips
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[Flags]
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protected enum FpSkips
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{
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None = 0,
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@ -300,7 +304,7 @@ namespace Ryujinx.Tests.Cpu
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IfNaND = 2,
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IfUnderflow = 4,
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IfOverflow = 8
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IfOverflow = 8,
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}
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protected enum FpTolerances
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@ -308,15 +312,15 @@ namespace Ryujinx.Tests.Cpu
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None,
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UpToOneUlpsS,
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UpToOneUlpsD
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UpToOneUlpsD,
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}
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protected void CompareAgainstUnicorn(
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Fpsr fpsrMask = Fpsr.None,
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FpSkips fpSkips = FpSkips.None,
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Fpsr fpsrMask = Fpsr.None,
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FpSkips fpSkips = FpSkips.None,
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FpTolerances fpTolerances = FpTolerances.None)
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{
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if (IgnoreAllExcept_FpsrQc)
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if (_ignoreAllExceptFpsrQc)
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{
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fpsrMask &= Fpsr.Qc;
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}
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@ -326,6 +330,7 @@ namespace Ryujinx.Tests.Cpu
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ManageFpSkips(fpSkips);
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}
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#pragma warning disable IDE0055 // Disable formatting
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Assert.That(_context.GetX(0), Is.EqualTo(_unicornEmu.X[0]), "X0");
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Assert.That(_context.GetX(1), Is.EqualTo(_unicornEmu.X[1]), "X1");
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Assert.That(_context.GetX(2), Is.EqualTo(_unicornEmu.X[2]), "X2");
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@ -358,6 +363,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(_context.GetX(29), Is.EqualTo(_unicornEmu.X[29]));
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Assert.That(_context.GetX(30), Is.EqualTo(_unicornEmu.X[30]));
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Assert.That(_context.GetX(31), Is.EqualTo(_unicornEmu.SP), "X31");
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#pragma warning restore IDE0055
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if (fpTolerances == FpTolerances.None)
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{
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@ -367,6 +373,8 @@ namespace Ryujinx.Tests.Cpu
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{
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ManageFpTolerances(fpTolerances);
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}
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#pragma warning disable IDE0055 // Disable formatting
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Assert.That(V128ToSimdValue(_context.GetV(1)), Is.EqualTo(_unicornEmu.Q[1]), "V1");
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Assert.That(V128ToSimdValue(_context.GetV(2)), Is.EqualTo(_unicornEmu.Q[2]), "V2");
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Assert.That(V128ToSimdValue(_context.GetV(3)), Is.EqualTo(_unicornEmu.Q[3]), "V3");
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@ -409,6 +417,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That((int)_context.Fpcr, Is.EqualTo(_unicornEmu.Fpcr), "Fpcr");
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Assert.That((int)_context.Fpsr & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpsr & (int)fpsrMask), "Fpsr");
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#pragma warning restore IDE0055
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if (_usingMemory)
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{
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@ -455,7 +464,7 @@ namespace Ryujinx.Tests.Cpu
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private void ManageFpTolerances(FpTolerances fpTolerances)
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{
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bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
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bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
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bool IsNormalOrSubnormalD(double d) => double.IsNormal(d) || double.IsSubnormal(d);
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if (!Is.EqualTo(_unicornEmu.Q[0]).ApplyTo(V128ToSimdValue(_context.GetV(0))).IsSuccess)
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@ -467,13 +476,13 @@ namespace Ryujinx.Tests.Cpu
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{
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Assert.Multiple(() =>
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{
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Assert.That (_context.GetV(0).Extract<float>(0),
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Assert.That(_context.GetV(0).Extract<float>(0),
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Is.EqualTo(_unicornEmu.Q[0].GetFloat(0)).Within(1).Ulps, "V0[0]");
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Assert.That (_context.GetV(0).Extract<float>(1),
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Assert.That(_context.GetV(0).Extract<float>(1),
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Is.EqualTo(_unicornEmu.Q[0].GetFloat(1)).Within(1).Ulps, "V0[1]");
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Assert.That (_context.GetV(0).Extract<float>(2),
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Assert.That(_context.GetV(0).Extract<float>(2),
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Is.EqualTo(_unicornEmu.Q[0].GetFloat(2)).Within(1).Ulps, "V0[2]");
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Assert.That (_context.GetV(0).Extract<float>(3),
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Assert.That(_context.GetV(0).Extract<float>(3),
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Is.EqualTo(_unicornEmu.Q[0].GetFloat(3)).Within(1).Ulps, "V0[3]");
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});
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@ -492,9 +501,9 @@ namespace Ryujinx.Tests.Cpu
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{
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Assert.Multiple(() =>
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{
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Assert.That (_context.GetV(0).Extract<double>(0),
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Assert.That(_context.GetV(0).Extract<double>(0),
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Is.EqualTo(_unicornEmu.Q[0].GetDouble(0)).Within(1).Ulps, "V0[0]");
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Assert.That (_context.GetV(0).Extract<double>(1),
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Assert.That(_context.GetV(0).Extract<double>(1),
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Is.EqualTo(_unicornEmu.Q[0].GetDouble(1)).Within(1).Ulps, "V0[1]");
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});
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@ -513,13 +522,13 @@ namespace Ryujinx.Tests.Cpu
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return new SimdValue(value.Extract<ulong>(0), value.Extract<ulong>(1));
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}
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protected static V128 MakeVectorScalar(float value) => new V128(value);
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protected static V128 MakeVectorScalar(double value) => new V128(value);
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protected static V128 MakeVectorScalar(float value) => new(value);
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protected static V128 MakeVectorScalar(double value) => new(value);
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protected static V128 MakeVectorE0(ulong e0) => new V128(e0, 0);
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protected static V128 MakeVectorE1(ulong e1) => new V128(0, e1);
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protected static V128 MakeVectorE0(ulong e0) => new(e0, 0);
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protected static V128 MakeVectorE1(ulong e1) => new(0, e1);
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protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new V128(e0, e1);
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protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new(e0, e1);
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protected static ulong GetVectorE0(V128 vector) => vector.Extract<ulong>(0);
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protected static ulong GetVectorE1(V128 vector) => vector.Extract<ulong>(1);
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@ -528,8 +537,9 @@ namespace Ryujinx.Tests.Cpu
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{
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uint rnd;
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do rnd = TestContext.CurrentContext.Random.NextUShort();
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while (( rnd & 0x7C00u) == 0u ||
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do
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rnd = TestContext.CurrentContext.Random.NextUShort();
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while ((rnd & 0x7C00u) == 0u ||
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(~rnd & 0x7C00u) == 0u);
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return (ushort)rnd;
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@ -539,7 +549,8 @@ namespace Ryujinx.Tests.Cpu
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{
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uint rnd;
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do rnd = TestContext.CurrentContext.Random.NextUShort();
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do
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rnd = TestContext.CurrentContext.Random.NextUShort();
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while ((rnd & 0x03FFu) == 0u);
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return (ushort)(rnd & 0x83FFu);
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@ -549,8 +560,9 @@ namespace Ryujinx.Tests.Cpu
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{
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uint rnd;
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do rnd = TestContext.CurrentContext.Random.NextUInt();
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while (( rnd & 0x7F800000u) == 0u ||
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do
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rnd = TestContext.CurrentContext.Random.NextUInt();
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while ((rnd & 0x7F800000u) == 0u ||
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(~rnd & 0x7F800000u) == 0u);
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return rnd;
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@ -560,7 +572,8 @@ namespace Ryujinx.Tests.Cpu
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{
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uint rnd;
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do rnd = TestContext.CurrentContext.Random.NextUInt();
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do
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rnd = TestContext.CurrentContext.Random.NextUInt();
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while ((rnd & 0x007FFFFFu) == 0u);
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return rnd & 0x807FFFFFu;
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@ -570,8 +583,9 @@ namespace Ryujinx.Tests.Cpu
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{
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ulong rnd;
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do rnd = TestContext.CurrentContext.Random.NextULong();
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while (( rnd & 0x7FF0000000000000ul) == 0ul ||
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do
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rnd = TestContext.CurrentContext.Random.NextULong();
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||||
while ((rnd & 0x7FF0000000000000ul) == 0ul ||
|
||||
(~rnd & 0x7FF0000000000000ul) == 0ul);
|
||||
|
||||
return rnd;
|
||||
|
|
@ -581,10 +595,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
ulong rnd;
|
||||
|
||||
do rnd = TestContext.CurrentContext.Random.NextULong();
|
||||
do
|
||||
rnd = TestContext.CurrentContext.Random.NextULong();
|
||||
while ((rnd & 0x000FFFFFFFFFFFFFul) == 0ul);
|
||||
|
||||
return rnd & 0x800FFFFFFFFFFFFFul;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue