mirror of
https://github.com/pound-emu/pound.git
synced 2025-12-11 07:36:57 +00:00
temp commit
Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar
parent
2e2b5df20c
commit
09ed3ca7ab
5 changed files with 157 additions and 58 deletions
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@ -97,7 +97,6 @@ add_executable(Pound
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add_subdirectory(3rd_Party)
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add_subdirectory(src/common)
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add_subdirectory(src/frontend)
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add_subdirectory(src/host)
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add_subdirectory(src/jit)
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add_subdirectory(src/pvm)
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@ -110,7 +109,7 @@ add_subdirectory(src/targets/switch1/hardware)
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include(TestBigEndian)
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TEST_BIG_ENDIAN(WORDS_BIGENDIAN)
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list(APPEND POUND_PROJECT_TARGETS common frontend host pvm)
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list(APPEND POUND_PROJECT_TARGETS common host pvm)
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foreach(TARGET ${POUND_PROJECT_TARGETS})
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# Apply Endianness definitions to all our targets.
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if(WORDS_BIGENDIAN)
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@ -149,7 +148,6 @@ set_property(TARGET Pound PROPERTY CMAKE_INTERPROCEDURAL_OPTIMIZATION_RELEASE TR
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target_link_libraries(Pound PRIVATE
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common
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frontend
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host
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jit
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pvm
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@ -1,6 +1,6 @@
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#include "arm32.h"
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#include <string.h>
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#include "common/passert.h"
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#include <string.h>
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#define LOG_MODULE "jit"
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#include "common/logging.h"
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@ -9,18 +9,19 @@ namespace pound::jit::decoder
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{
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/* Increase value as more instructions get implemented */
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#define INSTRUCTION_ARRAY_CAPACITY 4
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arm32_decoder_t g_arm32_decoder = {};
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#define HASH_TABLE_INVALID_INDEX 0xFFFF
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/*
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* ============================================================================
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* Foward Declarations
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* ============================================================================
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*/
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void arm32_add_instruction(arm32_decoder_t* decoder, const char* name, const char* bitstring, arm32_handler_fn handler);
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void arm32_ADD_imm_handler(arm32_decoder_t* decoder, arm32_instruction_t instruction);
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void arm32_add_instruction(arm32_decoder_t* decoder, const char* name, const char* bitstring);
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void arm32_parse_bitstring(const char* bitstring, uint32_t* mask, uint32_t* expected);
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void arm32_grow_instructions_array(arm32_decoder_t* decoder, size_t new_capacity);
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uint32_t arm32_generate_hash_seed(uint32_t mask, uint32_t expected);
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/*
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* ============================================================================
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@ -38,7 +39,7 @@ void arm32_init(pound::host::memory::arena_t allocator, arm32_decoder_t* decoder
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/* Setup Instructions array.*/
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size_t instructions_array_size = INSTRUCTION_ARRAY_CAPACITY * sizeof(arm32_instruction_info_t);
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PVM_ASSERT(instructions_array_size <= decoder->allocator.capacity);
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LOG_TRACE("Growing instructions array to %d bytes", instructions_array_size);
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LOG_TRACE("Allocated %d bytes to instructions array", instructions_array_size);
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void* new_ptr = pound::host::memory::arena_allocate(&decoder->allocator, instructions_array_size);
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PVM_ASSERT(nullptr != new_ptr);
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@ -47,12 +48,105 @@ void arm32_init(pound::host::memory::arena_t allocator, arm32_decoder_t* decoder
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decoder->instruction_capacity = INSTRUCTION_ARRAY_CAPACITY;
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/* Add all Arm32 instructions */
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#define INST(fn, name, bitstring) arm32_add_instruction(decoder, name, bitstring, &arm32_##fn##_handler);
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#define INST(fn, name, bitstring) arm32_add_instruction(decoder, name, bitstring);
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#include "./arm32.inc"
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#undef INST
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LOG_TRACE("Initializing perfect hash parameters for %zu instructions", decoder->instruction_count);
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/* Start with table size as next power of 2 >= count * 2 */
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uint16_t table_size = 1U;
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while (table_size < decoder->instruction_count * 2)
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{
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table_size <<= 1U;
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}
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uint16_t mask = table_size - 1;
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size_t slots_used_size = table_size * sizeof(bool);
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bool* slots_used = (bool*)pound::host::memory::arena_allocate(&decoder->allocator, slots_used_size);
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PVM_ASSERT(nullptr != slots_used);
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LOG_TRACE("Allocated %d bytes to hash slots used array", slots_used_size);
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uint16_t shift = 0;
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bool perfect_hash_generated = false;
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for (; shift < 16; ++shift)
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{
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bool collision_free = true;
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(void)memset(slots_used, false, slots_used_size);
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uint16_t hash;
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for (size_t i = 0; i < decoder->instruction_count; ++i)
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{
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uint32_t hash_seed =
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arm32_generate_hash_seed(decoder->instructions[i].mask, decoder->instructions[i].expected);
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/*
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* Now we need to convert the 32-bit hash seed into an index within our hash table.
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* We right shift by `shift` bits. Different shift values produce different hash distributions. We found
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* the shift value that ensures no two instructions map to the same hash table slot.
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*/
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hash = ((hash_seed >> shift) & mask);
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if (true == slots_used[hash])
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{
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LOG_TRACE("Instruction %s: Collision detected at slot %u for shift %u", decoder->instructions[i].name,
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hash, shift);
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collision_free = false;
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break;
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}
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slots_used[hash] = true;
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LOG_TRACE("Instruction %s: Collision-free hash %u found for shift %u", decoder->instructions[i].name, hash,
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shift);
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}
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if (true == collision_free)
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{
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perfect_hash_generated = true;
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break;
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}
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}
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PVM_ASSERT_MSG(true == perfect_hash_generated, "Failed to generate perfect hash - no collision-free hash found");
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LOG_TRACE("Perfect hash parameters: shift=%u, mask=0x%04x, table_size=%u", shift, mask, table_size);
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size_t hash_table_size = table_size * sizeof(uint16_t);
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uint16_t* hash_table = (uint16_t*)pound::host::memory::arena_allocate(&decoder->allocator, hash_table_size);
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PVM_ASSERT(nullptr != hash_table);
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LOG_TRACE("Allocated %zu bytes to hash table", hash_table_size);
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/* Initialize hash table with invalid indices */
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for (size_t i = 0; i < table_size; ++i)
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{
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hash_table[i] = HASH_TABLE_INVALID_INDEX;
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}
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for (size_t i = 0; i < decoder->instruction_count; ++i)
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{
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uint32_t hash_seed = arm32_generate_hash_seed(decoder->instructions[i].mask, decoder->instructions[i].expected);
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uint32_t hash = (hash_seed >> shift) & mask;
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PVM_ASSERT_MSG(HASH_TABLE_INVALID_INDEX == hash_table[hash], "Hash collision detected");
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PVM_ASSERT(i < 0xFFFF);
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hash_table[hash] = (uint16_t)i;
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LOG_TRACE("Instruction '%s' hashed to slot %u", decoder->instructions[i].name, hash);
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}
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decoder->perfect_hash.hash_shift = shift;
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decoder->perfect_hash.hash_mask = mask;
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decoder->perfect_hash.table_size = table_size;
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decoder->perfect_hash.hash_table = hash_table;
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}
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void arm32_add_instruction(arm32_decoder_t* decoder, const char* name, const char* bitstring, arm32_handler_fn handler)
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arm32_instruction_info_t* arm32_decode(arm32_decoder_t* decoder, uint32_t instruction)
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{
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}
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/*
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* ============================================================================
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* Private Functions
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* ============================================================================
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*/
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void arm32_add_instruction(arm32_decoder_t* decoder, const char* name, const char* bitstring)
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{
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PVM_ASSERT(nullptr != decoder);
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PVM_ASSERT(nullptr != decoder->allocator.data);
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@ -60,44 +154,25 @@ void arm32_add_instruction(arm32_decoder_t* decoder, const char* name, const cha
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PVM_ASSERT(nullptr != bitstring);
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PVM_ASSERT(decoder->instruction_count < decoder->instruction_capacity);
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arm32_opcode_t mask = 0;
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arm32_opcode_t expected = 0;
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uint32_t mask = 0;
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uint32_t expected = 0;
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arm32_parse_bitstring(bitstring, &mask, &expected);
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arm32_instruction_info_t* info = &decoder->instructions[decoder->instruction_count];
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PVM_ASSERT(nullptr != info);
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info->name = name;
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info->mask = mask;
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info->expected = expected;
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info->handler = handler;
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/* Calculate priority based on number of fixed bits. */
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info->priority = 0;
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for (int i = 0; i < 32; ++i)
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{
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if ((mask >> i) & 1)
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{
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++info->priority;
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}
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}
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info->priority = (uint8_t)__builtin_popcount(mask);
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++decoder->instruction_count;
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LOG_TRACE("========================================");
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LOG_TRACE("Instruction Registered: %s", info->name);
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LOG_TRACE("Mask: 0x%08X", info->mask);
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LOG_TRACE("Expected: 0x%08X", info->expected);
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LOG_TRACE("Priority: %d", info->priority);
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LOG_TRACE("========================================");
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/* TODO(GloriousTacoo:jit): Add instruction to lookup table. */
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}
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void arm32_ADD_imm_handler(arm32_decoder_t* decoder, arm32_instruction_t instruction) {}
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/*
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* ============================================================================
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* Private Functions
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* ============================================================================
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*/
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void arm32_parse_bitstring(const char* bitstring, uint32_t* mask, uint32_t* expected)
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{
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@ -109,7 +184,7 @@ void arm32_parse_bitstring(const char* bitstring, uint32_t* mask, uint32_t* expe
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*mask = 0;
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*expected = 0;
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uint8_t instruction_size_bits = 32;
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for (int i = 0; (i < instruction_size_bits) && (bitstring[i] != '\0'); ++i)
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for (unsigned int i = 0; (i < instruction_size_bits) && (bitstring[i] != '\0'); ++i)
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{
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uint32_t bit_position = 31 - i;
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switch (bitstring[i])
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@ -135,4 +210,36 @@ void arm32_parse_bitstring(const char* bitstring, uint32_t* mask, uint32_t* expe
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}
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}
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uint32_t arm32_generate_hash_seed(uint32_t mask, uint32_t expected)
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{
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/*
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* XOR combines the mask (which bits matter) and expected value (what those btis should be)
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* into a single 32-bit value that uniquely represents this instruction pattern.
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* Example: ADD instruction might have mask=0x0FF00000, expected=0x00200000
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* value = 0x0FF00000 ^ 0x00200000 = 0x0FD00000;
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*/
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uint32_t value = mask ^ expected;
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/*
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* First bit mixing round - break up patterns in the value.
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* We need to eliminate patterns (like trailing zeroes) that cause collisions.
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* We do this by mixing the high bits (16-31) with the low bits (0-15).
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*
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* We then multiply a magic number to further scrambles the bits to ensure good distribution.
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*/
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value = ((value >> 16) ^ value) * 0x45d9f3b;
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/*
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* Second bit mixing round to ensire thorough mixing
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*/
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value = ((value >> 16) ^ value) * 0x45d9f3b;
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/*
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* Final mixing. The result is our hash seed - a 32-bit number that uniquely represents this instruction.
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*/
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value = (value >> 16) ^ value;
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return value;
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}
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} // namespace pound::jit::decoder
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@ -7,17 +7,22 @@
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namespace pound::jit::decoder
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{
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typedef uint32_t arm32_opcode_t;
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typedef uint32_t arm32_instruction_t;
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typedef struct arm32_decoder arm32_decoder_t;
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typedef void (*arm32_handler_fn)(arm32_decoder_t* decoder, arm32_instruction_t instruction);
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typedef void (*arm32_handler_fn)(arm32_decoder_t* decoder, uint32_t instruction);
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typedef struct
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{
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uint16_t* hash_table;
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uint16_t hash_shift;
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uint16_t hash_mask;
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uint16_t table_size;
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} arm32_perfect_hash_t;
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typedef struct
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{
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const char* name;
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arm32_opcode_t mask;
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arm32_opcode_t expected;
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uint32_t mask;
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uint32_t expected;
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arm32_handler_fn handler;
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/* Use to order instructions in the lookup table. The more specific
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@ -27,27 +32,15 @@ typedef struct
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struct arm32_decoder
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{
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arm32_perfect_hash_t perfect_hash;
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pound::host::memory::arena_t allocator;
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arm32_instruction_info_t* instructions;
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size_t instruction_count;
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size_t instruction_capacity;
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struct
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{
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arm32_instruction_info_t** bucket;
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size_t count;
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size_t capacity;
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} lookup_table[4096]; /* 2^12 entries. */
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};
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extern arm32_decoder_t g_arm32_decoder;
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void arm32_init(pound::host::memory::arena_t allocator, arm32_decoder_t* decoder);
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void arm32_add_instruction(arm32_decoder_t* decoder, const char* name, arm32_opcode_t mask, arm32_opcode_t expected,
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arm32_handler_fn handler);
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void arm32_ADD_imm_handler(arm32_decoder_t* decoder, arm32_instruction_t instruction);
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} // namespace pound::jit::decoder
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#endif // POUND_JIT_DECODER_ARM32_H
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}
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#endif // POUND_JIT_DECODER_ARM32_H
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@ -64,7 +64,7 @@ INST(ADD_imm, "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv") // v1
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//INST(SBC_imm, "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv") // v1
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//INST(SBC_reg, "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm") // v1
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//INST(SBC_rsr, "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm") // v1
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//INST(SUB_imm, "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv") // v1
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INST(SUB_imm, "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv") // v1
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//INST(SUB_reg, "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm") // v1
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//INST(SUB_rsr, "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm") // v1
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//INST(TEQ_imm, "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv") // v1
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@ -20,7 +20,8 @@
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int main()
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{
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pound::host::memory::arena_t arena = pound::host::memory::arena_init(256);
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pound::jit::decoder::arm32_init(arena, £::jit::decoder::g_arm32_decoder);
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pound::jit::decoder::arm32_decoder_t decoder = {};
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pound::jit::decoder::arm32_init(arena, &decoder);
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#if 0
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gui::window_t window = {.data = nullptr, .gl_context = nullptr};
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(void)gui::window_init(&window, "Pound Emulator", 640, 480);
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Loading…
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Reference in a new issue