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jit/interpreter: Organize ifdefs

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Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar 2025-12-06 01:47:38 -04:00
parent b9b62574bf
commit 0d957968df
No known key found for this signature in database
GPG key ID: 04307C401999C596
5 changed files with 333 additions and 280 deletions
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5
scripts/generate_jit_assets.py
View file

@ -179,13 +179,12 @@ def write_interpreter_handler_table(path, instructions):
print(f"Generating interpreter handler table: {path}")
seen = set()
with open(path, "w") as f:
f.write("/* GENERATED FILE - DO NOT EDIT */\n")
f.write("/* This file is generated by scripts/generate_jit_assets.py */\n")
for inst in instructions:
enum_name = f"PVM_A32_OP_{inst.name.upper()}"
if enum_name not in seen:
f.write(f" [{enum_name}] = &&HANDLER_{enum_name},\n")
f.write(f" [{enum_name}] = &&{enum_name},\n")
seen.add(enum_name)
f.write(f" [PVM_A32_OP_STOP] = &&PVM_A32_OP_STOP,\n")
def write_interpreter_handler_skeletons(path, instructions):

503
src/jit/interpreter/arm32/handler_table.inc
View file

@ -1,252 +1,251 @@
/* GENERATED FILE - DO NOT EDIT */
/* This file is generated by scripts/generate_jit_assets.py */
[PVM_A32_OP_DMB] = &&HANDLER_PVM_A32_OP_DMB,
[PVM_A32_OP_DSB] = &&HANDLER_PVM_A32_OP_DSB,
[PVM_A32_OP_ISB] = &&HANDLER_PVM_A32_OP_ISB,
[PVM_A32_OP_BLX_IMM] = &&HANDLER_PVM_A32_OP_BLX_IMM,
[PVM_A32_OP_BLX_REG] = &&HANDLER_PVM_A32_OP_BLX_REG,
[PVM_A32_OP_B] = &&HANDLER_PVM_A32_OP_B,
[PVM_A32_OP_BL] = &&HANDLER_PVM_A32_OP_BL,
[PVM_A32_OP_BX] = &&HANDLER_PVM_A32_OP_BX,
[PVM_A32_OP_BXJ] = &&HANDLER_PVM_A32_OP_BXJ,
[PVM_A32_OP_RFE] = &&HANDLER_PVM_A32_OP_RFE,
[PVM_A32_OP_SRS] = &&HANDLER_PVM_A32_OP_SRS,
[PVM_A32_OP_CPS] = &&HANDLER_PVM_A32_OP_CPS,
[PVM_A32_OP_SETEND] = &&HANDLER_PVM_A32_OP_SETEND,
[PVM_A32_OP_CRC32] = &&HANDLER_PVM_A32_OP_CRC32,
[PVM_A32_OP_CRC32C] = &&HANDLER_PVM_A32_OP_CRC32C,
[PVM_A32_OP_CDP] = &&HANDLER_PVM_A32_OP_CDP,
[PVM_A32_OP_MCR] = &&HANDLER_PVM_A32_OP_MCR,
[PVM_A32_OP_MCRR] = &&HANDLER_PVM_A32_OP_MCRR,
[PVM_A32_OP_MRC] = &&HANDLER_PVM_A32_OP_MRC,
[PVM_A32_OP_MRRC] = &&HANDLER_PVM_A32_OP_MRRC,
[PVM_A32_OP_LDC] = &&HANDLER_PVM_A32_OP_LDC,
[PVM_A32_OP_STC] = &&HANDLER_PVM_A32_OP_STC,
[PVM_A32_OP_ADC_IMM] = &&HANDLER_PVM_A32_OP_ADC_IMM,
[PVM_A32_OP_ADC_REG] = &&HANDLER_PVM_A32_OP_ADC_REG,
[PVM_A32_OP_ADC_RSR] = &&HANDLER_PVM_A32_OP_ADC_RSR,
[PVM_A32_OP_ADD_IMM] = &&HANDLER_PVM_A32_OP_ADD_IMM,
[PVM_A32_OP_ADD_REG] = &&HANDLER_PVM_A32_OP_ADD_REG,
[PVM_A32_OP_ADD_RSR] = &&HANDLER_PVM_A32_OP_ADD_RSR,
[PVM_A32_OP_AND_IMM] = &&HANDLER_PVM_A32_OP_AND_IMM,
[PVM_A32_OP_AND_REG] = &&HANDLER_PVM_A32_OP_AND_REG,
[PVM_A32_OP_AND_RSR] = &&HANDLER_PVM_A32_OP_AND_RSR,
[PVM_A32_OP_BIC_IMM] = &&HANDLER_PVM_A32_OP_BIC_IMM,
[PVM_A32_OP_BIC_REG] = &&HANDLER_PVM_A32_OP_BIC_REG,
[PVM_A32_OP_BIC_RSR] = &&HANDLER_PVM_A32_OP_BIC_RSR,
[PVM_A32_OP_CMN_IMM] = &&HANDLER_PVM_A32_OP_CMN_IMM,
[PVM_A32_OP_CMN_REG] = &&HANDLER_PVM_A32_OP_CMN_REG,
[PVM_A32_OP_CMN_RSR] = &&HANDLER_PVM_A32_OP_CMN_RSR,
[PVM_A32_OP_CMP_IMM] = &&HANDLER_PVM_A32_OP_CMP_IMM,
[PVM_A32_OP_CMP_REG] = &&HANDLER_PVM_A32_OP_CMP_REG,
[PVM_A32_OP_CMP_RSR] = &&HANDLER_PVM_A32_OP_CMP_RSR,
[PVM_A32_OP_EOR_IMM] = &&HANDLER_PVM_A32_OP_EOR_IMM,
[PVM_A32_OP_EOR_REG] = &&HANDLER_PVM_A32_OP_EOR_REG,
[PVM_A32_OP_EOR_RSR] = &&HANDLER_PVM_A32_OP_EOR_RSR,
[PVM_A32_OP_MOV_IMM] = &&HANDLER_PVM_A32_OP_MOV_IMM,
[PVM_A32_OP_MOV_REG] = &&HANDLER_PVM_A32_OP_MOV_REG,
[PVM_A32_OP_MOV_RSR] = &&HANDLER_PVM_A32_OP_MOV_RSR,
[PVM_A32_OP_MVN_IMM] = &&HANDLER_PVM_A32_OP_MVN_IMM,
[PVM_A32_OP_MVN_REG] = &&HANDLER_PVM_A32_OP_MVN_REG,
[PVM_A32_OP_MVN_RSR] = &&HANDLER_PVM_A32_OP_MVN_RSR,
[PVM_A32_OP_ORR_IMM] = &&HANDLER_PVM_A32_OP_ORR_IMM,
[PVM_A32_OP_ORR_REG] = &&HANDLER_PVM_A32_OP_ORR_REG,
[PVM_A32_OP_ORR_RSR] = &&HANDLER_PVM_A32_OP_ORR_RSR,
[PVM_A32_OP_RSB_IMM] = &&HANDLER_PVM_A32_OP_RSB_IMM,
[PVM_A32_OP_RSB_REG] = &&HANDLER_PVM_A32_OP_RSB_REG,
[PVM_A32_OP_RSB_RSR] = &&HANDLER_PVM_A32_OP_RSB_RSR,
[PVM_A32_OP_RSC_IMM] = &&HANDLER_PVM_A32_OP_RSC_IMM,
[PVM_A32_OP_RSC_REG] = &&HANDLER_PVM_A32_OP_RSC_REG,
[PVM_A32_OP_RSC_RSR] = &&HANDLER_PVM_A32_OP_RSC_RSR,
[PVM_A32_OP_SBC_IMM] = &&HANDLER_PVM_A32_OP_SBC_IMM,
[PVM_A32_OP_SBC_REG] = &&HANDLER_PVM_A32_OP_SBC_REG,
[PVM_A32_OP_SBC_RSR] = &&HANDLER_PVM_A32_OP_SBC_RSR,
[PVM_A32_OP_SUB_IMM] = &&HANDLER_PVM_A32_OP_SUB_IMM,
[PVM_A32_OP_SUB_REG] = &&HANDLER_PVM_A32_OP_SUB_REG,
[PVM_A32_OP_SUB_RSR] = &&HANDLER_PVM_A32_OP_SUB_RSR,
[PVM_A32_OP_TEQ_IMM] = &&HANDLER_PVM_A32_OP_TEQ_IMM,
[PVM_A32_OP_TEQ_REG] = &&HANDLER_PVM_A32_OP_TEQ_REG,
[PVM_A32_OP_TEQ_RSR] = &&HANDLER_PVM_A32_OP_TEQ_RSR,
[PVM_A32_OP_TST_IMM] = &&HANDLER_PVM_A32_OP_TST_IMM,
[PVM_A32_OP_TST_REG] = &&HANDLER_PVM_A32_OP_TST_REG,
[PVM_A32_OP_TST_RSR] = &&HANDLER_PVM_A32_OP_TST_RSR,
[PVM_A32_OP_BKPT] = &&HANDLER_PVM_A32_OP_BKPT,
[PVM_A32_OP_SVC] = &&HANDLER_PVM_A32_OP_SVC,
[PVM_A32_OP_UDF] = &&HANDLER_PVM_A32_OP_UDF,
[PVM_A32_OP_SXTB] = &&HANDLER_PVM_A32_OP_SXTB,
[PVM_A32_OP_SXTB16] = &&HANDLER_PVM_A32_OP_SXTB16,
[PVM_A32_OP_SXTH] = &&HANDLER_PVM_A32_OP_SXTH,
[PVM_A32_OP_SXTAB] = &&HANDLER_PVM_A32_OP_SXTAB,
[PVM_A32_OP_SXTAB16] = &&HANDLER_PVM_A32_OP_SXTAB16,
[PVM_A32_OP_SXTAH] = &&HANDLER_PVM_A32_OP_SXTAH,
[PVM_A32_OP_UXTB] = &&HANDLER_PVM_A32_OP_UXTB,
[PVM_A32_OP_UXTB16] = &&HANDLER_PVM_A32_OP_UXTB16,
[PVM_A32_OP_UXTH] = &&HANDLER_PVM_A32_OP_UXTH,
[PVM_A32_OP_UXTAB] = &&HANDLER_PVM_A32_OP_UXTAB,
[PVM_A32_OP_UXTAB16] = &&HANDLER_PVM_A32_OP_UXTAB16,
[PVM_A32_OP_UXTAH] = &&HANDLER_PVM_A32_OP_UXTAH,
[PVM_A32_OP_PLD_IMM] = &&HANDLER_PVM_A32_OP_PLD_IMM,
[PVM_A32_OP_PLD_REG] = &&HANDLER_PVM_A32_OP_PLD_REG,
[PVM_A32_OP_SEV] = &&HANDLER_PVM_A32_OP_SEV,
[PVM_A32_OP_SEVL] = &&HANDLER_PVM_A32_OP_SEVL,
[PVM_A32_OP_WFE] = &&HANDLER_PVM_A32_OP_WFE,
[PVM_A32_OP_WFI] = &&HANDLER_PVM_A32_OP_WFI,
[PVM_A32_OP_YIELD] = &&HANDLER_PVM_A32_OP_YIELD,
[PVM_A32_OP_NOP] = &&HANDLER_PVM_A32_OP_NOP,
[PVM_A32_OP_CLREX] = &&HANDLER_PVM_A32_OP_CLREX,
[PVM_A32_OP_SWP] = &&HANDLER_PVM_A32_OP_SWP,
[PVM_A32_OP_SWPB] = &&HANDLER_PVM_A32_OP_SWPB,
[PVM_A32_OP_STL] = &&HANDLER_PVM_A32_OP_STL,
[PVM_A32_OP_STLEX] = &&HANDLER_PVM_A32_OP_STLEX,
[PVM_A32_OP_STREX] = &&HANDLER_PVM_A32_OP_STREX,
[PVM_A32_OP_LDA] = &&HANDLER_PVM_A32_OP_LDA,
[PVM_A32_OP_LDAEX] = &&HANDLER_PVM_A32_OP_LDAEX,
[PVM_A32_OP_LDREX] = &&HANDLER_PVM_A32_OP_LDREX,
[PVM_A32_OP_STLEXD] = &&HANDLER_PVM_A32_OP_STLEXD,
[PVM_A32_OP_STREXD] = &&HANDLER_PVM_A32_OP_STREXD,
[PVM_A32_OP_LDAEXD] = &&HANDLER_PVM_A32_OP_LDAEXD,
[PVM_A32_OP_LDREXD] = &&HANDLER_PVM_A32_OP_LDREXD,
[PVM_A32_OP_STLB] = &&HANDLER_PVM_A32_OP_STLB,
[PVM_A32_OP_STLEXB] = &&HANDLER_PVM_A32_OP_STLEXB,
[PVM_A32_OP_STREXB] = &&HANDLER_PVM_A32_OP_STREXB,
[PVM_A32_OP_LDAB] = &&HANDLER_PVM_A32_OP_LDAB,
[PVM_A32_OP_LDAEXB] = &&HANDLER_PVM_A32_OP_LDAEXB,
[PVM_A32_OP_LDREXB] = &&HANDLER_PVM_A32_OP_LDREXB,
[PVM_A32_OP_STLH] = &&HANDLER_PVM_A32_OP_STLH,
[PVM_A32_OP_STLEXH] = &&HANDLER_PVM_A32_OP_STLEXH,
[PVM_A32_OP_STREXH] = &&HANDLER_PVM_A32_OP_STREXH,
[PVM_A32_OP_LDAH] = &&HANDLER_PVM_A32_OP_LDAH,
[PVM_A32_OP_LDAEXH] = &&HANDLER_PVM_A32_OP_LDAEXH,
[PVM_A32_OP_LDREXH] = &&HANDLER_PVM_A32_OP_LDREXH,
[PVM_A32_OP_LDRBT] = &&HANDLER_PVM_A32_OP_LDRBT,
[PVM_A32_OP_LDRHT] = &&HANDLER_PVM_A32_OP_LDRHT,
[PVM_A32_OP_LDRSBT] = &&HANDLER_PVM_A32_OP_LDRSBT,
[PVM_A32_OP_LDRSHT] = &&HANDLER_PVM_A32_OP_LDRSHT,
[PVM_A32_OP_LDRT] = &&HANDLER_PVM_A32_OP_LDRT,
[PVM_A32_OP_STRBT] = &&HANDLER_PVM_A32_OP_STRBT,
[PVM_A32_OP_STRHT] = &&HANDLER_PVM_A32_OP_STRHT,
[PVM_A32_OP_STRT] = &&HANDLER_PVM_A32_OP_STRT,
[PVM_A32_OP_LDR_LIT] = &&HANDLER_PVM_A32_OP_LDR_LIT,
[PVM_A32_OP_LDR_IMM] = &&HANDLER_PVM_A32_OP_LDR_IMM,
[PVM_A32_OP_LDR_REG] = &&HANDLER_PVM_A32_OP_LDR_REG,
[PVM_A32_OP_LDRB_LIT] = &&HANDLER_PVM_A32_OP_LDRB_LIT,
[PVM_A32_OP_LDRB_IMM] = &&HANDLER_PVM_A32_OP_LDRB_IMM,
[PVM_A32_OP_LDRB_REG] = &&HANDLER_PVM_A32_OP_LDRB_REG,
[PVM_A32_OP_LDRD_LIT] = &&HANDLER_PVM_A32_OP_LDRD_LIT,
[PVM_A32_OP_LDRD_IMM] = &&HANDLER_PVM_A32_OP_LDRD_IMM,
[PVM_A32_OP_LDRD_REG] = &&HANDLER_PVM_A32_OP_LDRD_REG,
[PVM_A32_OP_LDRH_LIT] = &&HANDLER_PVM_A32_OP_LDRH_LIT,
[PVM_A32_OP_LDRH_IMM] = &&HANDLER_PVM_A32_OP_LDRH_IMM,
[PVM_A32_OP_LDRH_REG] = &&HANDLER_PVM_A32_OP_LDRH_REG,
[PVM_A32_OP_LDRSB_LIT] = &&HANDLER_PVM_A32_OP_LDRSB_LIT,
[PVM_A32_OP_LDRSB_IMM] = &&HANDLER_PVM_A32_OP_LDRSB_IMM,
[PVM_A32_OP_LDRSB_REG] = &&HANDLER_PVM_A32_OP_LDRSB_REG,
[PVM_A32_OP_LDRSH_LIT] = &&HANDLER_PVM_A32_OP_LDRSH_LIT,
[PVM_A32_OP_LDRSH_IMM] = &&HANDLER_PVM_A32_OP_LDRSH_IMM,
[PVM_A32_OP_LDRSH_REG] = &&HANDLER_PVM_A32_OP_LDRSH_REG,
[PVM_A32_OP_STR_IMM] = &&HANDLER_PVM_A32_OP_STR_IMM,
[PVM_A32_OP_STR_REG] = &&HANDLER_PVM_A32_OP_STR_REG,
[PVM_A32_OP_STRB_IMM] = &&HANDLER_PVM_A32_OP_STRB_IMM,
[PVM_A32_OP_STRB_REG] = &&HANDLER_PVM_A32_OP_STRB_REG,
[PVM_A32_OP_STRD_IMM] = &&HANDLER_PVM_A32_OP_STRD_IMM,
[PVM_A32_OP_STRD_REG] = &&HANDLER_PVM_A32_OP_STRD_REG,
[PVM_A32_OP_STRH_IMM] = &&HANDLER_PVM_A32_OP_STRH_IMM,
[PVM_A32_OP_STRH_REG] = &&HANDLER_PVM_A32_OP_STRH_REG,
[PVM_A32_OP_LDM] = &&HANDLER_PVM_A32_OP_LDM,
[PVM_A32_OP_LDMDA] = &&HANDLER_PVM_A32_OP_LDMDA,
[PVM_A32_OP_LDMDB] = &&HANDLER_PVM_A32_OP_LDMDB,
[PVM_A32_OP_LDMIB] = &&HANDLER_PVM_A32_OP_LDMIB,
[PVM_A32_OP_LDM_USR] = &&HANDLER_PVM_A32_OP_LDM_USR,
[PVM_A32_OP_LDM_ERET] = &&HANDLER_PVM_A32_OP_LDM_ERET,
[PVM_A32_OP_STM] = &&HANDLER_PVM_A32_OP_STM,
[PVM_A32_OP_STMDA] = &&HANDLER_PVM_A32_OP_STMDA,
[PVM_A32_OP_STMDB] = &&HANDLER_PVM_A32_OP_STMDB,
[PVM_A32_OP_STMIB] = &&HANDLER_PVM_A32_OP_STMIB,
[PVM_A32_OP_STM_USR] = &&HANDLER_PVM_A32_OP_STM_USR,
[PVM_A32_OP_BFC] = &&HANDLER_PVM_A32_OP_BFC,
[PVM_A32_OP_BFI] = &&HANDLER_PVM_A32_OP_BFI,
[PVM_A32_OP_CLZ] = &&HANDLER_PVM_A32_OP_CLZ,
[PVM_A32_OP_MOVT] = &&HANDLER_PVM_A32_OP_MOVT,
[PVM_A32_OP_MOVW] = &&HANDLER_PVM_A32_OP_MOVW,
[PVM_A32_OP_SBFX] = &&HANDLER_PVM_A32_OP_SBFX,
[PVM_A32_OP_SEL] = &&HANDLER_PVM_A32_OP_SEL,
[PVM_A32_OP_UBFX] = &&HANDLER_PVM_A32_OP_UBFX,
[PVM_A32_OP_USAD8] = &&HANDLER_PVM_A32_OP_USAD8,
[PVM_A32_OP_USADA8] = &&HANDLER_PVM_A32_OP_USADA8,
[PVM_A32_OP_PKHBT] = &&HANDLER_PVM_A32_OP_PKHBT,
[PVM_A32_OP_PKHTB] = &&HANDLER_PVM_A32_OP_PKHTB,
[PVM_A32_OP_RBIT] = &&HANDLER_PVM_A32_OP_RBIT,
[PVM_A32_OP_REV] = &&HANDLER_PVM_A32_OP_REV,
[PVM_A32_OP_REV16] = &&HANDLER_PVM_A32_OP_REV16,
[PVM_A32_OP_REVSH] = &&HANDLER_PVM_A32_OP_REVSH,
[PVM_A32_OP_SSAT] = &&HANDLER_PVM_A32_OP_SSAT,
[PVM_A32_OP_SSAT16] = &&HANDLER_PVM_A32_OP_SSAT16,
[PVM_A32_OP_USAT] = &&HANDLER_PVM_A32_OP_USAT,
[PVM_A32_OP_USAT16] = &&HANDLER_PVM_A32_OP_USAT16,
[PVM_A32_OP_SDIV] = &&HANDLER_PVM_A32_OP_SDIV,
[PVM_A32_OP_UDIV] = &&HANDLER_PVM_A32_OP_UDIV,
[PVM_A32_OP_MLA] = &&HANDLER_PVM_A32_OP_MLA,
[PVM_A32_OP_MLS] = &&HANDLER_PVM_A32_OP_MLS,
[PVM_A32_OP_MUL] = &&HANDLER_PVM_A32_OP_MUL,
[PVM_A32_OP_SMLAL] = &&HANDLER_PVM_A32_OP_SMLAL,
[PVM_A32_OP_SMULL] = &&HANDLER_PVM_A32_OP_SMULL,
[PVM_A32_OP_UMAAL] = &&HANDLER_PVM_A32_OP_UMAAL,
[PVM_A32_OP_UMLAL] = &&HANDLER_PVM_A32_OP_UMLAL,
[PVM_A32_OP_UMULL] = &&HANDLER_PVM_A32_OP_UMULL,
[PVM_A32_OP_SMLALXY] = &&HANDLER_PVM_A32_OP_SMLALXY,
[PVM_A32_OP_SMLAXY] = &&HANDLER_PVM_A32_OP_SMLAXY,
[PVM_A32_OP_SMULXY] = &&HANDLER_PVM_A32_OP_SMULXY,
[PVM_A32_OP_SMLAWY] = &&HANDLER_PVM_A32_OP_SMLAWY,
[PVM_A32_OP_SMULWY] = &&HANDLER_PVM_A32_OP_SMULWY,
[PVM_A32_OP_SMMUL] = &&HANDLER_PVM_A32_OP_SMMUL,
[PVM_A32_OP_SMMLA] = &&HANDLER_PVM_A32_OP_SMMLA,
[PVM_A32_OP_SMMLS] = &&HANDLER_PVM_A32_OP_SMMLS,
[PVM_A32_OP_SMUAD] = &&HANDLER_PVM_A32_OP_SMUAD,
[PVM_A32_OP_SMLAD] = &&HANDLER_PVM_A32_OP_SMLAD,
[PVM_A32_OP_SMLALD] = &&HANDLER_PVM_A32_OP_SMLALD,
[PVM_A32_OP_SMUSD] = &&HANDLER_PVM_A32_OP_SMUSD,
[PVM_A32_OP_SMLSD] = &&HANDLER_PVM_A32_OP_SMLSD,
[PVM_A32_OP_SMLSLD] = &&HANDLER_PVM_A32_OP_SMLSLD,
[PVM_A32_OP_SADD8] = &&HANDLER_PVM_A32_OP_SADD8,
[PVM_A32_OP_SADD16] = &&HANDLER_PVM_A32_OP_SADD16,
[PVM_A32_OP_SASX] = &&HANDLER_PVM_A32_OP_SASX,
[PVM_A32_OP_SSAX] = &&HANDLER_PVM_A32_OP_SSAX,
[PVM_A32_OP_SSUB8] = &&HANDLER_PVM_A32_OP_SSUB8,
[PVM_A32_OP_SSUB16] = &&HANDLER_PVM_A32_OP_SSUB16,
[PVM_A32_OP_UADD8] = &&HANDLER_PVM_A32_OP_UADD8,
[PVM_A32_OP_UADD16] = &&HANDLER_PVM_A32_OP_UADD16,
[PVM_A32_OP_UASX] = &&HANDLER_PVM_A32_OP_UASX,
[PVM_A32_OP_USAX] = &&HANDLER_PVM_A32_OP_USAX,
[PVM_A32_OP_USUB8] = &&HANDLER_PVM_A32_OP_USUB8,
[PVM_A32_OP_USUB16] = &&HANDLER_PVM_A32_OP_USUB16,
[PVM_A32_OP_QADD8] = &&HANDLER_PVM_A32_OP_QADD8,
[PVM_A32_OP_QADD16] = &&HANDLER_PVM_A32_OP_QADD16,
[PVM_A32_OP_QASX] = &&HANDLER_PVM_A32_OP_QASX,
[PVM_A32_OP_QSAX] = &&HANDLER_PVM_A32_OP_QSAX,
[PVM_A32_OP_QSUB8] = &&HANDLER_PVM_A32_OP_QSUB8,
[PVM_A32_OP_QSUB16] = &&HANDLER_PVM_A32_OP_QSUB16,
[PVM_A32_OP_UQADD8] = &&HANDLER_PVM_A32_OP_UQADD8,
[PVM_A32_OP_UQADD16] = &&HANDLER_PVM_A32_OP_UQADD16,
[PVM_A32_OP_UQASX] = &&HANDLER_PVM_A32_OP_UQASX,
[PVM_A32_OP_UQSAX] = &&HANDLER_PVM_A32_OP_UQSAX,
[PVM_A32_OP_UQSUB8] = &&HANDLER_PVM_A32_OP_UQSUB8,
[PVM_A32_OP_UQSUB16] = &&HANDLER_PVM_A32_OP_UQSUB16,
[PVM_A32_OP_SHADD8] = &&HANDLER_PVM_A32_OP_SHADD8,
[PVM_A32_OP_SHADD16] = &&HANDLER_PVM_A32_OP_SHADD16,
[PVM_A32_OP_SHASX] = &&HANDLER_PVM_A32_OP_SHASX,
[PVM_A32_OP_SHSAX] = &&HANDLER_PVM_A32_OP_SHSAX,
[PVM_A32_OP_SHSUB8] = &&HANDLER_PVM_A32_OP_SHSUB8,
[PVM_A32_OP_SHSUB16] = &&HANDLER_PVM_A32_OP_SHSUB16,
[PVM_A32_OP_UHADD8] = &&HANDLER_PVM_A32_OP_UHADD8,
[PVM_A32_OP_UHADD16] = &&HANDLER_PVM_A32_OP_UHADD16,
[PVM_A32_OP_UHASX] = &&HANDLER_PVM_A32_OP_UHASX,
[PVM_A32_OP_UHSAX] = &&HANDLER_PVM_A32_OP_UHSAX,
[PVM_A32_OP_UHSUB8] = &&HANDLER_PVM_A32_OP_UHSUB8,
[PVM_A32_OP_UHSUB16] = &&HANDLER_PVM_A32_OP_UHSUB16,
[PVM_A32_OP_QADD] = &&HANDLER_PVM_A32_OP_QADD,
[PVM_A32_OP_QSUB] = &&HANDLER_PVM_A32_OP_QSUB,
[PVM_A32_OP_QDADD] = &&HANDLER_PVM_A32_OP_QDADD,
[PVM_A32_OP_QDSUB] = &&HANDLER_PVM_A32_OP_QDSUB,
[PVM_A32_OP_MRS] = &&HANDLER_PVM_A32_OP_MRS,
[PVM_A32_OP_MSR_IMM] = &&HANDLER_PVM_A32_OP_MSR_IMM,
[PVM_A32_OP_MSR_REG] = &&HANDLER_PVM_A32_OP_MSR_REG,
[PVM_A32_OP_DMB] = &&PVM_A32_OP_DMB,
[PVM_A32_OP_DSB] = &&PVM_A32_OP_DSB,
[PVM_A32_OP_ISB] = &&PVM_A32_OP_ISB,
[PVM_A32_OP_BLX_IMM] = &&PVM_A32_OP_BLX_IMM,
[PVM_A32_OP_BLX_REG] = &&PVM_A32_OP_BLX_REG,
[PVM_A32_OP_B] = &&PVM_A32_OP_B,
[PVM_A32_OP_BL] = &&PVM_A32_OP_BL,
[PVM_A32_OP_BX] = &&PVM_A32_OP_BX,
[PVM_A32_OP_BXJ] = &&PVM_A32_OP_BXJ,
[PVM_A32_OP_RFE] = &&PVM_A32_OP_RFE,
[PVM_A32_OP_SRS] = &&PVM_A32_OP_SRS,
[PVM_A32_OP_CPS] = &&PVM_A32_OP_CPS,
[PVM_A32_OP_SETEND] = &&PVM_A32_OP_SETEND,
[PVM_A32_OP_CRC32] = &&PVM_A32_OP_CRC32,
[PVM_A32_OP_CRC32C] = &&PVM_A32_OP_CRC32C,
[PVM_A32_OP_CDP] = &&PVM_A32_OP_CDP,
[PVM_A32_OP_MCR] = &&PVM_A32_OP_MCR,
[PVM_A32_OP_MCRR] = &&PVM_A32_OP_MCRR,
[PVM_A32_OP_MRC] = &&PVM_A32_OP_MRC,
[PVM_A32_OP_MRRC] = &&PVM_A32_OP_MRRC,
[PVM_A32_OP_LDC] = &&PVM_A32_OP_LDC,
[PVM_A32_OP_STC] = &&PVM_A32_OP_STC,
[PVM_A32_OP_ADC_IMM] = &&PVM_A32_OP_ADC_IMM,
[PVM_A32_OP_ADC_REG] = &&PVM_A32_OP_ADC_REG,
[PVM_A32_OP_ADC_RSR] = &&PVM_A32_OP_ADC_RSR,
[PVM_A32_OP_ADD_IMM] = &&PVM_A32_OP_ADD_IMM,
[PVM_A32_OP_ADD_REG] = &&PVM_A32_OP_ADD_REG,
[PVM_A32_OP_ADD_RSR] = &&PVM_A32_OP_ADD_RSR,
[PVM_A32_OP_AND_IMM] = &&PVM_A32_OP_AND_IMM,
[PVM_A32_OP_AND_REG] = &&PVM_A32_OP_AND_REG,
[PVM_A32_OP_AND_RSR] = &&PVM_A32_OP_AND_RSR,
[PVM_A32_OP_BIC_IMM] = &&PVM_A32_OP_BIC_IMM,
[PVM_A32_OP_BIC_REG] = &&PVM_A32_OP_BIC_REG,
[PVM_A32_OP_BIC_RSR] = &&PVM_A32_OP_BIC_RSR,
[PVM_A32_OP_CMN_IMM] = &&PVM_A32_OP_CMN_IMM,
[PVM_A32_OP_CMN_REG] = &&PVM_A32_OP_CMN_REG,
[PVM_A32_OP_CMN_RSR] = &&PVM_A32_OP_CMN_RSR,
[PVM_A32_OP_CMP_IMM] = &&PVM_A32_OP_CMP_IMM,
[PVM_A32_OP_CMP_REG] = &&PVM_A32_OP_CMP_REG,
[PVM_A32_OP_CMP_RSR] = &&PVM_A32_OP_CMP_RSR,
[PVM_A32_OP_EOR_IMM] = &&PVM_A32_OP_EOR_IMM,
[PVM_A32_OP_EOR_REG] = &&PVM_A32_OP_EOR_REG,
[PVM_A32_OP_EOR_RSR] = &&PVM_A32_OP_EOR_RSR,
[PVM_A32_OP_MOV_IMM] = &&PVM_A32_OP_MOV_IMM,
[PVM_A32_OP_MOV_REG] = &&PVM_A32_OP_MOV_REG,
[PVM_A32_OP_MOV_RSR] = &&PVM_A32_OP_MOV_RSR,
[PVM_A32_OP_MVN_IMM] = &&PVM_A32_OP_MVN_IMM,
[PVM_A32_OP_MVN_REG] = &&PVM_A32_OP_MVN_REG,
[PVM_A32_OP_MVN_RSR] = &&PVM_A32_OP_MVN_RSR,
[PVM_A32_OP_ORR_IMM] = &&PVM_A32_OP_ORR_IMM,
[PVM_A32_OP_ORR_REG] = &&PVM_A32_OP_ORR_REG,
[PVM_A32_OP_ORR_RSR] = &&PVM_A32_OP_ORR_RSR,
[PVM_A32_OP_RSB_IMM] = &&PVM_A32_OP_RSB_IMM,
[PVM_A32_OP_RSB_REG] = &&PVM_A32_OP_RSB_REG,
[PVM_A32_OP_RSB_RSR] = &&PVM_A32_OP_RSB_RSR,
[PVM_A32_OP_RSC_IMM] = &&PVM_A32_OP_RSC_IMM,
[PVM_A32_OP_RSC_REG] = &&PVM_A32_OP_RSC_REG,
[PVM_A32_OP_RSC_RSR] = &&PVM_A32_OP_RSC_RSR,
[PVM_A32_OP_SBC_IMM] = &&PVM_A32_OP_SBC_IMM,
[PVM_A32_OP_SBC_REG] = &&PVM_A32_OP_SBC_REG,
[PVM_A32_OP_SBC_RSR] = &&PVM_A32_OP_SBC_RSR,
[PVM_A32_OP_SUB_IMM] = &&PVM_A32_OP_SUB_IMM,
[PVM_A32_OP_SUB_REG] = &&PVM_A32_OP_SUB_REG,
[PVM_A32_OP_SUB_RSR] = &&PVM_A32_OP_SUB_RSR,
[PVM_A32_OP_TEQ_IMM] = &&PVM_A32_OP_TEQ_IMM,
[PVM_A32_OP_TEQ_REG] = &&PVM_A32_OP_TEQ_REG,
[PVM_A32_OP_TEQ_RSR] = &&PVM_A32_OP_TEQ_RSR,
[PVM_A32_OP_TST_IMM] = &&PVM_A32_OP_TST_IMM,
[PVM_A32_OP_TST_REG] = &&PVM_A32_OP_TST_REG,
[PVM_A32_OP_TST_RSR] = &&PVM_A32_OP_TST_RSR,
[PVM_A32_OP_BKPT] = &&PVM_A32_OP_BKPT,
[PVM_A32_OP_SVC] = &&PVM_A32_OP_SVC,
[PVM_A32_OP_UDF] = &&PVM_A32_OP_UDF,
[PVM_A32_OP_SXTB] = &&PVM_A32_OP_SXTB,
[PVM_A32_OP_SXTB16] = &&PVM_A32_OP_SXTB16,
[PVM_A32_OP_SXTH] = &&PVM_A32_OP_SXTH,
[PVM_A32_OP_SXTAB] = &&PVM_A32_OP_SXTAB,
[PVM_A32_OP_SXTAB16] = &&PVM_A32_OP_SXTAB16,
[PVM_A32_OP_SXTAH] = &&PVM_A32_OP_SXTAH,
[PVM_A32_OP_UXTB] = &&PVM_A32_OP_UXTB,
[PVM_A32_OP_UXTB16] = &&PVM_A32_OP_UXTB16,
[PVM_A32_OP_UXTH] = &&PVM_A32_OP_UXTH,
[PVM_A32_OP_UXTAB] = &&PVM_A32_OP_UXTAB,
[PVM_A32_OP_UXTAB16] = &&PVM_A32_OP_UXTAB16,
[PVM_A32_OP_UXTAH] = &&PVM_A32_OP_UXTAH,
[PVM_A32_OP_PLD_IMM] = &&PVM_A32_OP_PLD_IMM,
[PVM_A32_OP_PLD_REG] = &&PVM_A32_OP_PLD_REG,
[PVM_A32_OP_SEV] = &&PVM_A32_OP_SEV,
[PVM_A32_OP_SEVL] = &&PVM_A32_OP_SEVL,
[PVM_A32_OP_WFE] = &&PVM_A32_OP_WFE,
[PVM_A32_OP_WFI] = &&PVM_A32_OP_WFI,
[PVM_A32_OP_YIELD] = &&PVM_A32_OP_YIELD,
[PVM_A32_OP_NOP] = &&PVM_A32_OP_NOP,
[PVM_A32_OP_CLREX] = &&PVM_A32_OP_CLREX,
[PVM_A32_OP_SWP] = &&PVM_A32_OP_SWP,
[PVM_A32_OP_SWPB] = &&PVM_A32_OP_SWPB,
[PVM_A32_OP_STL] = &&PVM_A32_OP_STL,
[PVM_A32_OP_STLEX] = &&PVM_A32_OP_STLEX,
[PVM_A32_OP_STREX] = &&PVM_A32_OP_STREX,
[PVM_A32_OP_LDA] = &&PVM_A32_OP_LDA,
[PVM_A32_OP_LDAEX] = &&PVM_A32_OP_LDAEX,
[PVM_A32_OP_LDREX] = &&PVM_A32_OP_LDREX,
[PVM_A32_OP_STLEXD] = &&PVM_A32_OP_STLEXD,
[PVM_A32_OP_STREXD] = &&PVM_A32_OP_STREXD,
[PVM_A32_OP_LDAEXD] = &&PVM_A32_OP_LDAEXD,
[PVM_A32_OP_LDREXD] = &&PVM_A32_OP_LDREXD,
[PVM_A32_OP_STLB] = &&PVM_A32_OP_STLB,
[PVM_A32_OP_STLEXB] = &&PVM_A32_OP_STLEXB,
[PVM_A32_OP_STREXB] = &&PVM_A32_OP_STREXB,
[PVM_A32_OP_LDAB] = &&PVM_A32_OP_LDAB,
[PVM_A32_OP_LDAEXB] = &&PVM_A32_OP_LDAEXB,
[PVM_A32_OP_LDREXB] = &&PVM_A32_OP_LDREXB,
[PVM_A32_OP_STLH] = &&PVM_A32_OP_STLH,
[PVM_A32_OP_STLEXH] = &&PVM_A32_OP_STLEXH,
[PVM_A32_OP_STREXH] = &&PVM_A32_OP_STREXH,
[PVM_A32_OP_LDAH] = &&PVM_A32_OP_LDAH,
[PVM_A32_OP_LDAEXH] = &&PVM_A32_OP_LDAEXH,
[PVM_A32_OP_LDREXH] = &&PVM_A32_OP_LDREXH,
[PVM_A32_OP_LDRBT] = &&PVM_A32_OP_LDRBT,
[PVM_A32_OP_LDRHT] = &&PVM_A32_OP_LDRHT,
[PVM_A32_OP_LDRSBT] = &&PVM_A32_OP_LDRSBT,
[PVM_A32_OP_LDRSHT] = &&PVM_A32_OP_LDRSHT,
[PVM_A32_OP_LDRT] = &&PVM_A32_OP_LDRT,
[PVM_A32_OP_STRBT] = &&PVM_A32_OP_STRBT,
[PVM_A32_OP_STRHT] = &&PVM_A32_OP_STRHT,
[PVM_A32_OP_STRT] = &&PVM_A32_OP_STRT,
[PVM_A32_OP_LDR_LIT] = &&PVM_A32_OP_LDR_LIT,
[PVM_A32_OP_LDR_IMM] = &&PVM_A32_OP_LDR_IMM,
[PVM_A32_OP_LDR_REG] = &&PVM_A32_OP_LDR_REG,
[PVM_A32_OP_LDRB_LIT] = &&PVM_A32_OP_LDRB_LIT,
[PVM_A32_OP_LDRB_IMM] = &&PVM_A32_OP_LDRB_IMM,
[PVM_A32_OP_LDRB_REG] = &&PVM_A32_OP_LDRB_REG,
[PVM_A32_OP_LDRD_LIT] = &&PVM_A32_OP_LDRD_LIT,
[PVM_A32_OP_LDRD_IMM] = &&PVM_A32_OP_LDRD_IMM,
[PVM_A32_OP_LDRD_REG] = &&PVM_A32_OP_LDRD_REG,
[PVM_A32_OP_LDRH_LIT] = &&PVM_A32_OP_LDRH_LIT,
[PVM_A32_OP_LDRH_IMM] = &&PVM_A32_OP_LDRH_IMM,
[PVM_A32_OP_LDRH_REG] = &&PVM_A32_OP_LDRH_REG,
[PVM_A32_OP_LDRSB_LIT] = &&PVM_A32_OP_LDRSB_LIT,
[PVM_A32_OP_LDRSB_IMM] = &&PVM_A32_OP_LDRSB_IMM,
[PVM_A32_OP_LDRSB_REG] = &&PVM_A32_OP_LDRSB_REG,
[PVM_A32_OP_LDRSH_LIT] = &&PVM_A32_OP_LDRSH_LIT,
[PVM_A32_OP_LDRSH_IMM] = &&PVM_A32_OP_LDRSH_IMM,
[PVM_A32_OP_LDRSH_REG] = &&PVM_A32_OP_LDRSH_REG,
[PVM_A32_OP_STR_IMM] = &&PVM_A32_OP_STR_IMM,
[PVM_A32_OP_STR_REG] = &&PVM_A32_OP_STR_REG,
[PVM_A32_OP_STRB_IMM] = &&PVM_A32_OP_STRB_IMM,
[PVM_A32_OP_STRB_REG] = &&PVM_A32_OP_STRB_REG,
[PVM_A32_OP_STRD_IMM] = &&PVM_A32_OP_STRD_IMM,
[PVM_A32_OP_STRD_REG] = &&PVM_A32_OP_STRD_REG,
[PVM_A32_OP_STRH_IMM] = &&PVM_A32_OP_STRH_IMM,
[PVM_A32_OP_STRH_REG] = &&PVM_A32_OP_STRH_REG,
[PVM_A32_OP_LDM] = &&PVM_A32_OP_LDM,
[PVM_A32_OP_LDMDA] = &&PVM_A32_OP_LDMDA,
[PVM_A32_OP_LDMDB] = &&PVM_A32_OP_LDMDB,
[PVM_A32_OP_LDMIB] = &&PVM_A32_OP_LDMIB,
[PVM_A32_OP_LDM_USR] = &&PVM_A32_OP_LDM_USR,
[PVM_A32_OP_LDM_ERET] = &&PVM_A32_OP_LDM_ERET,
[PVM_A32_OP_STM] = &&PVM_A32_OP_STM,
[PVM_A32_OP_STMDA] = &&PVM_A32_OP_STMDA,
[PVM_A32_OP_STMDB] = &&PVM_A32_OP_STMDB,
[PVM_A32_OP_STMIB] = &&PVM_A32_OP_STMIB,
[PVM_A32_OP_STM_USR] = &&PVM_A32_OP_STM_USR,
[PVM_A32_OP_BFC] = &&PVM_A32_OP_BFC,
[PVM_A32_OP_BFI] = &&PVM_A32_OP_BFI,
[PVM_A32_OP_CLZ] = &&PVM_A32_OP_CLZ,
[PVM_A32_OP_MOVT] = &&PVM_A32_OP_MOVT,
[PVM_A32_OP_MOVW] = &&PVM_A32_OP_MOVW,
[PVM_A32_OP_SBFX] = &&PVM_A32_OP_SBFX,
[PVM_A32_OP_SEL] = &&PVM_A32_OP_SEL,
[PVM_A32_OP_UBFX] = &&PVM_A32_OP_UBFX,
[PVM_A32_OP_USAD8] = &&PVM_A32_OP_USAD8,
[PVM_A32_OP_USADA8] = &&PVM_A32_OP_USADA8,
[PVM_A32_OP_PKHBT] = &&PVM_A32_OP_PKHBT,
[PVM_A32_OP_PKHTB] = &&PVM_A32_OP_PKHTB,
[PVM_A32_OP_RBIT] = &&PVM_A32_OP_RBIT,
[PVM_A32_OP_REV] = &&PVM_A32_OP_REV,
[PVM_A32_OP_REV16] = &&PVM_A32_OP_REV16,
[PVM_A32_OP_REVSH] = &&PVM_A32_OP_REVSH,
[PVM_A32_OP_SSAT] = &&PVM_A32_OP_SSAT,
[PVM_A32_OP_SSAT16] = &&PVM_A32_OP_SSAT16,
[PVM_A32_OP_USAT] = &&PVM_A32_OP_USAT,
[PVM_A32_OP_USAT16] = &&PVM_A32_OP_USAT16,
[PVM_A32_OP_SDIV] = &&PVM_A32_OP_SDIV,
[PVM_A32_OP_UDIV] = &&PVM_A32_OP_UDIV,
[PVM_A32_OP_MLA] = &&PVM_A32_OP_MLA,
[PVM_A32_OP_MLS] = &&PVM_A32_OP_MLS,
[PVM_A32_OP_MUL] = &&PVM_A32_OP_MUL,
[PVM_A32_OP_SMLAL] = &&PVM_A32_OP_SMLAL,
[PVM_A32_OP_SMULL] = &&PVM_A32_OP_SMULL,
[PVM_A32_OP_UMAAL] = &&PVM_A32_OP_UMAAL,
[PVM_A32_OP_UMLAL] = &&PVM_A32_OP_UMLAL,
[PVM_A32_OP_UMULL] = &&PVM_A32_OP_UMULL,
[PVM_A32_OP_SMLALXY] = &&PVM_A32_OP_SMLALXY,
[PVM_A32_OP_SMLAXY] = &&PVM_A32_OP_SMLAXY,
[PVM_A32_OP_SMULXY] = &&PVM_A32_OP_SMULXY,
[PVM_A32_OP_SMLAWY] = &&PVM_A32_OP_SMLAWY,
[PVM_A32_OP_SMULWY] = &&PVM_A32_OP_SMULWY,
[PVM_A32_OP_SMMUL] = &&PVM_A32_OP_SMMUL,
[PVM_A32_OP_SMMLA] = &&PVM_A32_OP_SMMLA,
[PVM_A32_OP_SMMLS] = &&PVM_A32_OP_SMMLS,
[PVM_A32_OP_SMUAD] = &&PVM_A32_OP_SMUAD,
[PVM_A32_OP_SMLAD] = &&PVM_A32_OP_SMLAD,
[PVM_A32_OP_SMLALD] = &&PVM_A32_OP_SMLALD,
[PVM_A32_OP_SMUSD] = &&PVM_A32_OP_SMUSD,
[PVM_A32_OP_SMLSD] = &&PVM_A32_OP_SMLSD,
[PVM_A32_OP_SMLSLD] = &&PVM_A32_OP_SMLSLD,
[PVM_A32_OP_SADD8] = &&PVM_A32_OP_SADD8,
[PVM_A32_OP_SADD16] = &&PVM_A32_OP_SADD16,
[PVM_A32_OP_SASX] = &&PVM_A32_OP_SASX,
[PVM_A32_OP_SSAX] = &&PVM_A32_OP_SSAX,
[PVM_A32_OP_SSUB8] = &&PVM_A32_OP_SSUB8,
[PVM_A32_OP_SSUB16] = &&PVM_A32_OP_SSUB16,
[PVM_A32_OP_UADD8] = &&PVM_A32_OP_UADD8,
[PVM_A32_OP_UADD16] = &&PVM_A32_OP_UADD16,
[PVM_A32_OP_UASX] = &&PVM_A32_OP_UASX,
[PVM_A32_OP_USAX] = &&PVM_A32_OP_USAX,
[PVM_A32_OP_USUB8] = &&PVM_A32_OP_USUB8,
[PVM_A32_OP_USUB16] = &&PVM_A32_OP_USUB16,
[PVM_A32_OP_QADD8] = &&PVM_A32_OP_QADD8,
[PVM_A32_OP_QADD16] = &&PVM_A32_OP_QADD16,
[PVM_A32_OP_QASX] = &&PVM_A32_OP_QASX,
[PVM_A32_OP_QSAX] = &&PVM_A32_OP_QSAX,
[PVM_A32_OP_QSUB8] = &&PVM_A32_OP_QSUB8,
[PVM_A32_OP_QSUB16] = &&PVM_A32_OP_QSUB16,
[PVM_A32_OP_UQADD8] = &&PVM_A32_OP_UQADD8,
[PVM_A32_OP_UQADD16] = &&PVM_A32_OP_UQADD16,
[PVM_A32_OP_UQASX] = &&PVM_A32_OP_UQASX,
[PVM_A32_OP_UQSAX] = &&PVM_A32_OP_UQSAX,
[PVM_A32_OP_UQSUB8] = &&PVM_A32_OP_UQSUB8,
[PVM_A32_OP_UQSUB16] = &&PVM_A32_OP_UQSUB16,
[PVM_A32_OP_SHADD8] = &&PVM_A32_OP_SHADD8,
[PVM_A32_OP_SHADD16] = &&PVM_A32_OP_SHADD16,
[PVM_A32_OP_SHASX] = &&PVM_A32_OP_SHASX,
[PVM_A32_OP_SHSAX] = &&PVM_A32_OP_SHSAX,
[PVM_A32_OP_SHSUB8] = &&PVM_A32_OP_SHSUB8,
[PVM_A32_OP_SHSUB16] = &&PVM_A32_OP_SHSUB16,
[PVM_A32_OP_UHADD8] = &&PVM_A32_OP_UHADD8,
[PVM_A32_OP_UHADD16] = &&PVM_A32_OP_UHADD16,
[PVM_A32_OP_UHASX] = &&PVM_A32_OP_UHASX,
[PVM_A32_OP_UHSAX] = &&PVM_A32_OP_UHSAX,
[PVM_A32_OP_UHSUB8] = &&PVM_A32_OP_UHSUB8,
[PVM_A32_OP_UHSUB16] = &&PVM_A32_OP_UHSUB16,
[PVM_A32_OP_QADD] = &&PVM_A32_OP_QADD,
[PVM_A32_OP_QSUB] = &&PVM_A32_OP_QSUB,
[PVM_A32_OP_QDADD] = &&PVM_A32_OP_QDADD,
[PVM_A32_OP_QDSUB] = &&PVM_A32_OP_QDSUB,
[PVM_A32_OP_MRS] = &&PVM_A32_OP_MRS,
[PVM_A32_OP_MSR_IMM] = &&PVM_A32_OP_MSR_IMM,
[PVM_A32_OP_MSR_REG] = &&PVM_A32_OP_MSR_REG,
[PVM_A32_OP_STOP] = &&PVM_A32_OP_STOP,

4
src/jit/interpreter/arm32/handlers.inc
View file

@ -1249,7 +1249,7 @@ HANDLER(PVM_A32_OP_MSR_REG): {
}
HANDLER(PVM_A32_OP_STOP): {
// TODO: Implement handler for PVM_A32_OP_STOP
DISPATCH();
printf("IT WORKS!\n");
return;
}

100
src/jit/interpreter/arm32/instruction.c
View file

@ -1,47 +1,101 @@
/*
* THIS FILE IS A WORK IN PROGRESS AND WILL BE RE-WRITTEN
* Defines pvm_jit_interpreter_instruction_t struct and its internal opcodes.
* Defines pvm_jit_interpreter_arm32_instruction_t struct and its internal
* opcodes.
*/
#include "frontend/decoder/arm32_opcodes.h"
#include "common/passert.h"
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
/*
* Computed gotos are a GCC/Clang extension that significantly improves
* interpreter performance by predicting branch targets.
*/
#if defined(__GNUC__) || defined(__clang__)
#define HANDLER(name) HANDLER_##name
#define DISPATCH() do { \
instr++; \
goto *dispatch_table[instr->opcode]; \
} while(0)
#define PVM_USE_COMPUTED_GOTO 1
#else
#define HANDLER(name) case name
#define DISPATCH() goto dispatch_loop
#define PVM_USE_COMPUTED_GOTO 0
#endif
typedef struct
{
uint32_t GPRs[16];
uint32_t PSTATE;
} pvm_jit_interpreter_arm32_cpu_state_t;
typedef struct
{
pvm_jit_decoder_arm32_opcode_t opcode;
} instruction_t;
} pvm_jit_interpreter_arm32_instruction_t;
void
temp(void)
temp (void)
{
instruction_t *instr = malloc(sizeof(*instr));
instr->opcode = PVM_A32_OP_STOP;
#if defined(__GNUC__) || defined(__clang__)
static const void* const dispatch_table[] = {
#include "handler_table.inc"
pvm_jit_interpreter_arm32_instruction_t *instr = calloc(3, sizeof(*instr));
instr->opcode = PVM_A32_OP_ADD_REG;
(++instr)->opcode = PVM_A32_OP_STOP;
/*
* Uses a jump table with address labels (&&LABEL) to dispatch directly to the
* handler.
*/
#if PVM_USE_COMPUTED_GOTO
/* The dispatch table contains the address of every label in handlers.inc */
static const void *const dispatch_table[] = {
#include "handler_table.inc"
};
// Initial dispatch
/*
* HANDLER macro defines the label target.
* DISPATCH macro increments IP and jumps to the next handler.
*/
#define HANDLER(name) name
#define DISPATCH() \
do \
{ \
instr++; \
goto *dispatch_table[instr->opcode]; \
} while (0)
/* Must perform the initial jump to start the race. */
goto *dispatch_table[instr->opcode];
/* Include the instruction logic */
#include "handlers.inc"
#undef HANDLER
#undef DISPATCH
/*
* Uses a standard switch statement. Slower due to bounds checking and lack of
* branch prediction, but 100% portable and safe.
*/
#else
dispatch_loop:
switch (instr->opcode) {
#endif
#include "handlers.inc"
/*
* HANDLER macro defines a switch case.
* DISPATCH macro jumps back to the switch statement.
*/
#define HANDLER(name) case name
#define DISPATCH() goto dispatch_loop
#if !defined(__GNUC__) && !defined(__clang__)
default: goto HANDLER_PVM_A32_OP_STOP;
dispatch_loop:
switch (instr->opcode)
{
/* Include the instruction logic */
#include "handlers.inc"
default:
PVM_ASSERT_MSG(
0, "Invalid Opcode in interpreter dispatch: %d", instr->opcode);
break;
}
#undef HANDLER
#undef DISPATCH
#endif
}

1
src/jit/interpreter/arm32/instruction.h Normal file
View file

@ -0,0 +1 @@
void temp(void);