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aarch64: fix include file in jit

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Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar 2025-08-10 02:42:27 -04:00
parent 59e812bc63
commit 1300cc1535
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GPG key ID: 04307C401999C596
2 changed files with 20 additions and 14 deletions
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27
core/JIT/jit.cpp
View file

@ -14,7 +14,8 @@
using JitFunc = void (*)(); using JitFunc = void (*)();
void JIT::translate_and_run(CPU& cpu) { void JIT::translate_and_run(CPU& cpu)
{
// TODO: Create REM Context // TODO: Create REM Context
create_rem_context(nullptr, nullptr, nullptr, nullptr, nullptr); create_rem_context(nullptr, nullptr, nullptr, nullptr, nullptr);
@ -28,32 +29,36 @@ void JIT::translate_and_run(CPU& cpu) {
size_t offset = 0; size_t offset = 0;
// Decode mock instructions from cpu.memory // Decode mock instructions from cpu.memory
if (cpu.memory[0] == 0x05) { // MOVZ placeholder if (cpu.memory[0] == 0x05)
code[offset++] = 0x48; // mov rax, imm64 { // MOVZ placeholder
code[offset++] = 0x48; // mov rax, imm64
code[offset++] = 0xB8; code[offset++] = 0xB8;
u64 imm = 5; u64 imm = 5;
std::memcpy(&code[offset], &imm, sizeof(imm)); std::memcpy(&code[offset], &imm, sizeof(imm));
offset += 8; offset += 8;
} }
if (cpu.memory[4] == 0x03) { // ADD placeholder if (cpu.memory[4] == 0x03)
code[offset++] = 0x48; // add rax, imm32 { // ADD placeholder
code[offset++] = 0x48; // add rax, imm32
code[offset++] = 0x05; code[offset++] = 0x05;
u32 addval = 3; u32 addval = 3;
std::memcpy(&code[offset], &addval, sizeof(addval)); std::memcpy(&code[offset], &addval, sizeof(addval));
offset += 4; offset += 4;
} }
code[offset++] = 0xC3; // ret code[offset++] = 0xC3; // ret
JitFunc fn = reinterpret_cast<JitFunc>(code); JitFunc fn = reinterpret_cast<JitFunc>(code);
u64 result; u64 result;
#if defined(__x86_64__) #if defined(__x86_64__)
asm volatile("call *%1\n" asm volatile(
"mov %%rax, %0\n" "call *%1\n"
: "=r"(result) "mov %%rax, %0\n"
: "r"(fn) : "=r"(result)
: "%rax"); : "r"(fn)
: "%rax");
#elif defined(__aarch64__) #elif defined(__aarch64__)
asm volatile("blr %1\n" asm volatile("blr %1\n"
"mov %0, x0\n" "mov %0, x0\n"

7
core/JIT/jit.h
View file

@ -2,9 +2,10 @@
#pragma once #pragma once
#include "ARM/cpu.h" #include "aarch64/isa.h"
class JIT { class JIT
public: {
public:
void translate_and_run(CPU& cpu); void translate_and_run(CPU& cpu);
}; };