From 4456e23f7c484490a88b454bbc494c1819db20ee Mon Sep 17 00:00:00 2001
From: Ronald Caesar <github43132@proton.me>
Date: Sun, 10 Aug 2025 19:01:26 -0400
Subject: [PATCH] aarch64: Add core state structure for vCPU emulation

Introduce the basic data structures required to manage the architectural
state of an emulated ARMv8 guest. This is a foundational patch for a
forthcoming emulator framework.

The core of this change is the `vcpu_state_t` structure, which holds
the essential user-visible state of a single virtual CPU (vCPU),
including the general-purpose registers, stack pointer, program counter,
and PSTATE.

The state for all vCPUs is aligned to the CPU L1 cache line. This design
choice ensures that there is no false sharing between physical host
cores running separate vCPU emulation threads.

Signed-off-by: Ronald Caesar <github43132@proton.me>
---
 core/aarch64/isa.cpp |  5 ++++-
 core/aarch64/isa.h   | 44 +++++++++++++++++++++++---------------------
 2 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/core/aarch64/isa.cpp b/core/aarch64/isa.cpp
index ed4ef51..791e31b 100755
--- a/core/aarch64/isa.cpp
+++ b/core/aarch64/isa.cpp
@@ -3,6 +3,9 @@
 
 void cpuTest()
 {
+    aarch64::vcpu_state_t vcpu_states[CPU_CORES] = {};
+
+    // Outdated Code
     CPU cpu;
     cpu.pc = 0;
 
@@ -14,4 +17,4 @@ void cpuTest()
 
     LOG_INFO(ARM, "{}", cpu.read_byte(0));
     cpu.print_debug_information();
-}
\ No newline at end of file
+}
diff --git a/core/aarch64/isa.h b/core/aarch64/isa.h
index 1e5236d..0d75500 100644
--- a/core/aarch64/isa.h
+++ b/core/aarch64/isa.h
@@ -3,38 +3,40 @@
 #pragma once
 
 #include <cstring>
+#include <cstdlib>
 
 #include "Base/Logging/Log.h"
 
 namespace aarch64
 {
-#define GPR_REGISTERS 32
-#define ZERO_REGISTER_INDEX 31
+/* AArch64 R0-R30 */
+#define GP_REGISTERS 31
+#define CACHE_LINE_SIZE 64
+#define CPU_CORES 8
 
-#define FPR_REGISTERS 32
-
-typedef struct
+/*
+ * vcpu_state_t - Holds the architectural state for an emulated vCPU.
+ * @r:      General purpose registers R0-R30.
+ * @pc:     Program Counter.
+ * @sp:     Stack Pointer.
+ * @pstate: Process State Register (NZCV flags, EL, etc.).
+ *
+ * This structure is aligned to the L1 cache line size to prevent false
+ * sharing when multiple host threads are emulating vCPUs on different
+ * physical cores.
+ */
+typedef struct alignas(CACHE_LINE_SIZE)
 {
-    uint64_t gpr[GPR_REGISTERS];
-    unsigned __int128 fpr[FPR_REGISTERS];
+    uint64_t r[GP_REGISTERS];
     uint64_t pc;
     uint64_t sp;
-} isa_t;
-
-uint64_t read_X(uint64_t* registers, size_t n);
-void adr(uint64_t* registers, size_t n, uint64_t pc, uint64_t offset);
-//=========================================================
-// Access Floating Point Registers
-//=========================================================
-
-uint8_t B(unsigned __int128 registers, size_t n);
-uint16_t H(unsigned __int128 registers, size_t n);
-uint32_t S(unsigned __int128 registers, size_t n);
-uint64_t D(unsigned __int128 registers, size_t n);
-unsigned __int128 Q(unsigned __int128 registers, size_t n);
-
+    uint32_t pstate;
+} vcpu_state_t;
 }  // namespace aarch64
 
+//=========================================================
+// OUTDATED CODE
+//=========================================================
 struct CPU
 {
     u64 regs[31] = {0};  // X0–X30