aarch64/kernel: Add synchronous exception entry logic

To handle faults such as data aborts, alignment faults, or supervisor
calls, the CPU must transition from the guest's context into a
privileged exception handler. This patch emulates the hardware sequence
for this entry process.

1. The vcpu_state_t struct includes the essential EL1 system registers
   required for exception handling (ELR_EL1, SPSR_EL1, ESR_EL1, FAR_EL1,
   and VBAR_EL1).

2. A new function, take_synchronous_exception(), is introduced. It
   models the requirements for entering an exception targeting EL1:
      - Saves the return address (PC) into ELR_EL1.
      - Saves the current proccess state (PSTATE) into SPSR_EL1.
      - Contructs the Exception Syndrome Register (ESR_EL1) from the
        provided Exception Class and ISS.
      - Saves the faulting address to FAR_EL1 for data aborts.
      - Updates the live PSTATE to a safe state for the handler.

This implementation is intentially partial. The final step of updating the
PC to jump to a handler in the guest's vector table (using VBAR_EL1) is
stubbed out. The vector table will contain assembly instructions so a
functional instruction decoder is required to fully complete the
exception handler.

Signed-off-by: Ronald Caesar <github43132@proton.me>

core/main.cpp

@@ -5,8 +5,8 @@
 #include <thread>
 
 #include "Base/Config.h"
+#include "Base/Logging/Log.h"
 #include "Base/Logging/Backend.h"
-#include "JIT/jit.h"
 #include "gui/gui.h"
 #include "memory/arena.h"
 
@@ -18,10 +18,6 @@
 
 int main()
 {
-    // This is meant to replace malloc() and its related functions.
-    // TODO(GloriousTaco:memory): Implement std::allocator for this custom allocator which allows it to manage the memory of C++ standard types like std::vector.
-    memory::arena_t arena = memory::arena_init(1024);
-
     Base::Log::Initialize();
     Base::Log::Start();