mirror of
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jit/decoder: move decoder to frontend/decoder
Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar
parent
fb7a2a6b32
commit
c235e57071
7 changed files with 7 additions and 7 deletions
34
src/jit/frontend/decoder/arm32.c
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34
src/jit/frontend/decoder/arm32.c
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#include "arm32.h"
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#include "arm32_table_generated.h"
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#include "common/passert.h"
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#include <string.h>
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#include <stdbool.h>
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#define LOG_MODULE "jit"
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#include "common/logging.h"
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const pvm_jit_decoder_arm32_instruction_info_t *
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pvm_jit_decoder_arm32_decode (const uint32_t instruction)
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{
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/* Extract hash key: Bits [27:20] and [7:4] */
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const uint32_t major = (instruction >> 20U) & 0xFFU;
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const uint32_t minor = (instruction >> 4U) & 0xFU;
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const uint16_t index = (uint16_t)((major << 4U) | minor);
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const decode_bucket_t *bucket = &g_decoder_lookup_table[index];
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for (size_t i = 0; i < bucket->count; ++i)
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{
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const pvm_jit_decoder_arm32_instruction_info_t *info = bucket->instructions[i];
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if ((instruction & info->mask) == info->expected)
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{
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return info;
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}
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}
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LOG_WARNING("Cannot decode instruction 0x%08X", instruction);
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return NULL;
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}
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62
src/jit/frontend/decoder/arm32.h
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62
src/jit/frontend/decoder/arm32.h
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/**
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* @file arm32.h
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* @brief A32 Instruction Decoder Interface.
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*
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* @details
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* This module provides the interface for decoding 32-bit ARM instructions
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* into internal metadata structures.
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*
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*/
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#ifndef POUND_JIT_DECODER_ARM32_H
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#define POUND_JIT_DECODER_ARM32_H
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#include <stdint.h>
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/*! @brief Represents static metadata associated with a specific ARM32
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* instruction. */
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typedef struct
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{
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/*! @brief The instruction mnemonic (e.g., "ADD", "LDR"). */
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const char *name;
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/*!
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* @brief The raw bitstring representation.
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* @details Used during initialization to calculate mask and expected
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* values.
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*/
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const char *bitstring;
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/*!
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* @brief The bitmask indicating which bits in the instruction word are
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* significant.
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* @details 1 = significant bit, 0 = variable field (register, immediate,
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* etc.).
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*/
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uint32_t mask;
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/*!
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* @brief The expected value of the instruction after applying the mask.
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* @details (instruction & mask) == expected.
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*/
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uint32_t expected;
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} pvm_jit_decoder_arm32_instruction_info_t;
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/*!
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* @brief Decodes a raw 32-bit ARM instruction.
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*
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* @details
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* Performs a hash lookup on the provided instruction word to find a matching
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* definition.
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*
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* @param[in] instruction The raw 32-bit ARM machine code to decode.
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*
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* @return A pointer to the instruction metadata if a match is found.
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* @return `nullptr` if the instruction is undefined or invalid.
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*
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* @post The returned pointer (if not null) points to static read-only memory.
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*/
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const pvm_jit_decoder_arm32_instruction_info_t *pvm_jit_decoder_arm32_decode(
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const uint32_t instruction);
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#endif // POUND_JIT_DECODER_ARM32_H
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316
src/jit/frontend/decoder/arm32.inc
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316
src/jit/frontend/decoder/arm32.inc
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@ -0,0 +1,316 @@
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// Barrier instructions
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INST(DMB, "DMB", "1111010101111111111100000101oooo") // v7
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INST(DSB, "DSB", "1111010101111111111100000100oooo") // v7
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INST(ISB, "ISB", "1111010101111111111100000110oooo") // v7
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// Branch instructions
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INST(BLX_imm, "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv") // v5
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INST(BLX_reg, "BLX (reg)", "cccc000100101111111111110011mmmm") // v5
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INST(B, "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv") // v1
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INST(BL, "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv") // v1
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INST(BX, "BX", "cccc000100101111111111110001mmmm") // v4T
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INST(BXJ, "BXJ", "cccc000100101111111111110010mmmm") // v5J
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// CRC32 instructions
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INST(CRC32, "CRC32", "cccc00010zz0nnnndddd00000100mmmm") // v8
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INST(CRC32C, "CRC32C", "cccc00010zz0nnnndddd00100100mmmm") // v8
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// Coprocessor instructions
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INST(CDP, "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM") // v2 (CDP2: v5)
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INST(LDC, "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv") // v2 (LDC2: v5)
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INST(MCR, "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM") // v2 (MCR2: v5)
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INST(MCRR, "MCRR", "cccc11000100uuuuttttppppooooMMMM") // v5E (MCRR2: v6)
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INST(MRC, "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM") // v2 (MRC2: v5)
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INST(MRRC, "MRRC", "cccc11000101uuuuttttppppooooMMMM") // v5E (MRRC2: v6)
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INST(STC, "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv") // v2 (STC2: v5)
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// Data Processing instructions
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INST(ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv") // v1
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INST(ADC_reg, "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm") // v1
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INST(ADC_rsr, "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm") // v1
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INST(ADD_imm, "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv") // v1
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INST(ADD_reg, "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm") // v1
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INST(ADD_rsr, "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm") // v1
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INST(AND_imm, "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv") // v1
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INST(AND_reg, "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm") // v1
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INST(AND_rsr, "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm") // v1
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INST(BIC_imm, "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv") // v1
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INST(BIC_reg, "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm") // v1
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INST(BIC_rsr, "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm") // v1
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INST(CMN_imm, "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv") // v1
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INST(CMN_reg, "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm") // v1
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INST(CMN_rsr, "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm") // v1
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INST(CMP_imm, "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv") // v1
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INST(CMP_reg, "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm") // v1
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INST(CMP_rsr, "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm") // v1
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INST(EOR_imm, "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv") // v1
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INST(EOR_reg, "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm") // v1
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INST(EOR_rsr, "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm") // v1
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INST(MOV_imm, "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv") // v1
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INST(MOV_reg, "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm") // v1
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INST(MOV_rsr, "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm") // v1
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INST(MVN_imm, "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv") // v1
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INST(MVN_reg, "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm") // v1
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INST(MVN_rsr, "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm") // v1
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INST(ORR_imm, "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv") // v1
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INST(ORR_reg, "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm") // v1
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INST(ORR_rsr, "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm") // v1
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INST(RSB_imm, "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv") // v1
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INST(RSB_reg, "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm") // v1
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INST(RSB_rsr, "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm") // v1
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INST(RSC_imm, "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv") // v1
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INST(RSC_reg, "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm") // v1
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INST(RSC_rsr, "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm") // v1
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INST(SBC_imm, "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv") // v1
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INST(SBC_reg, "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm") // v1
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INST(SBC_rsr, "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm") // v1
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INST(SUB_imm, "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv") // v1
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INST(SUB_reg, "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm") // v1
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INST(SUB_rsr, "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm") // v1
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INST(TEQ_imm, "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv") // v1
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INST(TEQ_reg, "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm") // v1
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INST(TEQ_rsr, "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm") // v1
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INST(TST_imm, "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv") // v1
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INST(TST_reg, "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm") // v1
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INST(TST_rsr, "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm") // v1
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// Exception Generating instructions
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INST(BKPT, "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv") // v5
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INST(SVC, "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv") // v1
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INST(UDF, "UDF", "111001111111------------1111----")
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// Extension instructions
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INST(SXTB, "SXTB", "cccc011010101111ddddrr000111mmmm") // v6
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INST(SXTB16, "SXTB16", "cccc011010001111ddddrr000111mmmm") // v6
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INST(SXTH, "SXTH", "cccc011010111111ddddrr000111mmmm") // v6
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INST(SXTAB, "SXTAB", "cccc01101010nnnnddddrr000111mmmm") // v6
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INST(SXTAB16, "SXTAB16", "cccc01101000nnnnddddrr000111mmmm") // v6
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INST(SXTAH, "SXTAH", "cccc01101011nnnnddddrr000111mmmm") // v6
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INST(UXTB, "UXTB", "cccc011011101111ddddrr000111mmmm") // v6
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INST(UXTB16, "UXTB16", "cccc011011001111ddddrr000111mmmm") // v6
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INST(UXTH, "UXTH", "cccc011011111111ddddrr000111mmmm") // v6
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INST(UXTAB, "UXTAB", "cccc01101110nnnnddddrr000111mmmm") // v6
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INST(UXTAB16, "UXTAB16", "cccc01101100nnnnddddrr000111mmmm") // v6
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INST(UXTAH, "UXTAH", "cccc01101111nnnnddddrr000111mmmm") // v6
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// Hint instructions
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INST(PLD_imm, "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii") // v5E for PLD; v7 for PLDW
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INST(PLD_reg, "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm") // v5E for PLD; v7 for PLDW
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INST(SEV, "SEV", "----0011001000001111000000000100") // v6K
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INST(SEVL, "SEVL", "----0011001000001111000000000101") // v8
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INST(WFE, "WFE", "----0011001000001111000000000010") // v6K
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INST(WFI, "WFI", "----0011001000001111000000000011") // v6K
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INST(YIELD, "YIELD", "----0011001000001111000000000001") // v6K
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INST(NOP, "Reserved Hint", "----0011001000001111------------")
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INST(NOP, "Reserved Hint", "----001100100000111100000000----")
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// Synchronization Primitive instructions
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INST(CLREX, "CLREX", "11110101011111111111000000011111") // v6K
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INST(SWP, "SWP", "cccc00010000nnnntttt00001001uuuu") // v2S (v6: Deprecated)
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INST(SWPB, "SWPB", "cccc00010100nnnntttt00001001uuuu") // v2S (v6: Deprecated)
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INST(STL, "STL", "cccc00011000nnnn111111001001tttt") // v8
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INST(STLEX, "STLEX", "cccc00011000nnnndddd11101001tttt") // v8
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INST(STREX, "STREX", "cccc00011000nnnndddd11111001mmmm") // v6
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INST(LDA, "LDA", "cccc00011001nnnndddd110010011111") // v8
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INST(LDAEX, "LDAEX", "cccc00011001nnnndddd111010011111") // v8
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INST(LDREX, "LDREX", "cccc00011001nnnndddd111110011111") // v6
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INST(STLEXD, "STLEXD", "cccc00011010nnnndddd11101001mmmm") // v8
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INST(STREXD, "STREXD", "cccc00011010nnnndddd11111001mmmm") // v6K
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INST(LDAEXD, "LDAEXD", "cccc00011011nnnndddd111010011111") // v8
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INST(LDREXD, "LDREXD", "cccc00011011nnnndddd111110011111") // v6K
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INST(STLB, "STLB", "cccc00011100nnnn111111001001tttt") // v8
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INST(STLEXB, "STLEXB", "cccc00011100nnnndddd11101001mmmm") // v8
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INST(STREXB, "STREXB", "cccc00011100nnnndddd11111001mmmm") // v6K
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INST(LDAB, "LDAB", "cccc00011101nnnndddd110010011111") // v8
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INST(LDAEXB, "LDAEXB", "cccc00011101nnnndddd111010011111") // v8
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INST(LDREXB, "LDREXB", "cccc00011101nnnndddd111110011111") // v6K
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INST(STLH, "STLH", "cccc00011110nnnn111111001001mmmm") // v8
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INST(STLEXH, "STLEXH", "cccc00011110nnnndddd11101001mmmm") // v8
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INST(STREXH, "STREXH", "cccc00011110nnnndddd11111001mmmm") // v6K
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INST(LDAH, "LDAH", "cccc00011111nnnndddd110010011111") // v8
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INST(LDAEXH, "LDAEXH", "cccc00011111nnnndddd111010011111") // v8
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INST(LDREXH, "LDREXH", "cccc00011111nnnndddd111110011111") // v6K
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// Load/Store instructions
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INST(LDRBT, "LDRBT (A1)", "----0100-111--------------------") // v1
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INST(LDRBT, "LDRBT (A2)", "----0110-111---------------0----") // v1
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INST(LDRHT, "LDRHT (A1)", "----0000-111------------1011----") // v6T2
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INST(LDRHT, "LDRHT (A1)", "----0000-1111111--------1011----") // v6T2
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INST(LDRHT, "LDRHT (A2)", "----0000-011--------00001011----") // v6T2
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INST(LDRSBT, "LDRSBT (A1)", "----0000-111------------1101----") // v6T2
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INST(LDRSBT, "LDRSBT (A2)", "----0000-011--------00001101----") // v6T2
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INST(LDRSHT, "LDRSHT (A1)", "----0000-111------------1111----") // v6T2
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INST(LDRSHT, "LDRSHT (A2)", "----0000-011--------00001111----") // v6T2
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INST(LDRT, "LDRT (A1)", "----0100-011--------------------") // v1
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INST(LDRT, "LDRT (A2)", "----0110-011---------------0----") // v1
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INST(STRBT, "STRBT (A1)", "----0100-110--------------------") // v1
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INST(STRBT, "STRBT (A2)", "----0110-110---------------0----") // v1
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INST(STRHT, "STRHT (A1)", "----0000-110------------1011----") // v6T2
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INST(STRHT, "STRHT (A2)", "----0000-010--------00001011----") // v6T2
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INST(STRT, "STRT (A1)", "----0100-010--------------------") // v1
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INST(STRT, "STRT (A2)", "----0110-010---------------0----") // v1
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INST(LDR_lit, "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv") // v1
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INST(LDR_imm, "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv") // v1
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INST(LDR_reg, "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm") // v1
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INST(LDRB_lit, "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv") // v1
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INST(LDRB_imm, "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv") // v1
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INST(LDRB_reg, "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm") // v1
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INST(LDRD_lit, "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv") // v5E
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INST(LDRD_imm, "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv") // v5E
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INST(LDRD_reg, "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm") // v5E
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INST(LDRH_lit, "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv") // v4
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INST(LDRH_imm, "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv") // v4
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INST(LDRH_reg, "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm") // v4
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INST(LDRSB_lit, "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv") // v4
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INST(LDRSB_imm, "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv") // v4
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INST(LDRSB_reg, "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm") // v4
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INST(LDRSH_lit, "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv") // v4
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INST(LDRSH_imm, "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv") // v4
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INST(LDRSH_reg, "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm") // v4
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INST(STR_imm, "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv") // v1
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INST(STR_reg, "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm") // v1
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INST(STRB_imm, "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv") // v1
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INST(STRB_reg, "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm") // v1
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INST(STRD_imm, "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv") // v5E
|
||||
INST(STRD_reg, "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm") // v5E
|
||||
INST(STRH_imm, "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv") // v4
|
||||
INST(STRH_reg, "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm") // v4
|
||||
|
||||
// Load/Store Multiple instructions
|
||||
INST(LDM, "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(LDMDA, "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(LDMDB, "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(LDMIB, "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(LDM_usr, "LDM (usr reg)", "----100--101--------------------") // v1
|
||||
INST(LDM_eret, "LDM (exce ret)", "----100--1-1----1---------------") // v1
|
||||
INST(STM, "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(STMDA, "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(STMDB, "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(STMIB, "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx") // v1
|
||||
INST(STM_usr, "STM (usr reg)", "----100--100--------------------") // v1
|
||||
|
||||
// Miscellaneous instructions
|
||||
INST(BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2
|
||||
INST(BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
|
||||
INST(CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5
|
||||
INST(MOVT, "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv") // v6T2
|
||||
INST(MOVW, "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv") // v6T2
|
||||
INST(NOP, "NOP", "----0011001000001111000000000000") // v6K
|
||||
INST(SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
|
||||
INST(SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6
|
||||
INST(UBFX, "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
|
||||
|
||||
// Unsigned Sum of Absolute Differences instructions
|
||||
INST(USAD8, "USAD8", "cccc01111000dddd1111mmmm0001nnnn") // v6
|
||||
INST(USADA8, "USADA8", "cccc01111000ddddaaaammmm0001nnnn") // v6
|
||||
|
||||
// Packing instructions
|
||||
INST(PKHBT, "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm") // v6K
|
||||
INST(PKHTB, "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm") // v6K
|
||||
|
||||
// Reversal instructions
|
||||
INST(RBIT, "RBIT", "cccc011011111111dddd11110011mmmm") // v6T2
|
||||
INST(REV, "REV", "cccc011010111111dddd11110011mmmm") // v6
|
||||
INST(REV16, "REV16", "cccc011010111111dddd11111011mmmm") // v6
|
||||
INST(REVSH, "REVSH", "cccc011011111111dddd11111011mmmm") // v6
|
||||
|
||||
// Saturation instructions
|
||||
INST(SSAT, "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn") // v6
|
||||
INST(SSAT16, "SSAT16", "cccc01101010vvvvdddd11110011nnnn") // v6
|
||||
INST(USAT, "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn") // v6
|
||||
INST(USAT16, "USAT16", "cccc01101110vvvvdddd11110011nnnn") // v6
|
||||
|
||||
// Divide instructions
|
||||
INST(SDIV, "SDIV", "cccc01110001dddd1111mmmm0001nnnn") // v7a
|
||||
INST(UDIV, "UDIV", "cccc01110011dddd1111mmmm0001nnnn") // v7a
|
||||
|
||||
// Multiply (Normal) instructions
|
||||
INST(MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn") // v2
|
||||
INST(MLS, "MLS", "cccc00000110ddddaaaammmm1001nnnn") // v6T2
|
||||
INST(MUL, "MUL", "cccc0000000Sdddd0000mmmm1001nnnn") // v2
|
||||
|
||||
// Multiply (Long) instructions
|
||||
INST(SMLAL, "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn") // v3M
|
||||
INST(SMULL, "SMULL", "cccc0000110Sddddaaaammmm1001nnnn") // v3M
|
||||
INST(UMAAL, "UMAAL", "cccc00000100ddddaaaammmm1001nnnn") // v6
|
||||
INST(UMLAL, "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn") // v3M
|
||||
INST(UMULL, "UMULL", "cccc0000100Sddddaaaammmm1001nnnn") // v3M
|
||||
|
||||
// Multiply (Halfword) instructions
|
||||
INST(SMLALxy, "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn") // v5xP
|
||||
INST(SMLAxy, "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn") // v5xP
|
||||
INST(SMULxy, "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn") // v5xP
|
||||
|
||||
// Multiply (Word by Halfword) instructions
|
||||
INST(SMLAWy, "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn") // v5xP
|
||||
INST(SMULWy, "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn") // v5xP
|
||||
|
||||
// Multiply (Most Significant Word) instructions
|
||||
INST(SMMUL, "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn") // v6
|
||||
INST(SMMLA, "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn") // v6
|
||||
INST(SMMLS, "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn") // v6
|
||||
|
||||
// Multiply (Dual) instructions
|
||||
INST(SMLAD, "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn") // v6
|
||||
INST(SMLALD, "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn") // v6
|
||||
INST(SMLSD, "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn") // v6
|
||||
INST(SMLSLD, "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn") // v6
|
||||
INST(SMUAD, "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn") // v6
|
||||
INST(SMUSD, "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn") // v6
|
||||
|
||||
// Parallel Add/Subtract (Modulo) instructions
|
||||
INST(SADD8, "SADD8", "cccc01100001nnnndddd11111001mmmm") // v6
|
||||
INST(SADD16, "SADD16", "cccc01100001nnnndddd11110001mmmm") // v6
|
||||
INST(SASX, "SASX", "cccc01100001nnnndddd11110011mmmm") // v6
|
||||
INST(SSAX, "SSAX", "cccc01100001nnnndddd11110101mmmm") // v6
|
||||
INST(SSUB8, "SSUB8", "cccc01100001nnnndddd11111111mmmm") // v6
|
||||
INST(SSUB16, "SSUB16", "cccc01100001nnnndddd11110111mmmm") // v6
|
||||
INST(UADD8, "UADD8", "cccc01100101nnnndddd11111001mmmm") // v6
|
||||
INST(UADD16, "UADD16", "cccc01100101nnnndddd11110001mmmm") // v6
|
||||
INST(UASX, "UASX", "cccc01100101nnnndddd11110011mmmm") // v6
|
||||
INST(USAX, "USAX", "cccc01100101nnnndddd11110101mmmm") // v6
|
||||
INST(USUB8, "USUB8", "cccc01100101nnnndddd11111111mmmm") // v6
|
||||
INST(USUB16, "USUB16", "cccc01100101nnnndddd11110111mmmm") // v6
|
||||
|
||||
// Parallel Add/Subtract (Saturating) instructions
|
||||
INST(QADD8, "QADD8", "cccc01100010nnnndddd11111001mmmm") // v6
|
||||
INST(QADD16, "QADD16", "cccc01100010nnnndddd11110001mmmm") // v6
|
||||
INST(QASX, "QASX", "cccc01100010nnnndddd11110011mmmm") // v6
|
||||
INST(QSAX, "QSAX", "cccc01100010nnnndddd11110101mmmm") // v6
|
||||
INST(QSUB8, "QSUB8", "cccc01100010nnnndddd11111111mmmm") // v6
|
||||
INST(QSUB16, "QSUB16", "cccc01100010nnnndddd11110111mmmm") // v6
|
||||
INST(UQADD8, "UQADD8", "cccc01100110nnnndddd11111001mmmm") // v6
|
||||
INST(UQADD16, "UQADD16", "cccc01100110nnnndddd11110001mmmm") // v6
|
||||
INST(UQASX, "UQASX", "cccc01100110nnnndddd11110011mmmm") // v6
|
||||
INST(UQSAX, "UQSAX", "cccc01100110nnnndddd11110101mmmm") // v6
|
||||
INST(UQSUB8, "UQSUB8", "cccc01100110nnnndddd11111111mmmm") // v6
|
||||
INST(UQSUB16, "UQSUB16", "cccc01100110nnnndddd11110111mmmm") // v6
|
||||
|
||||
// Parallel Add/Subtract (Halving) instructions
|
||||
INST(SHADD8, "SHADD8", "cccc01100011nnnndddd11111001mmmm") // v6
|
||||
INST(SHADD16, "SHADD16", "cccc01100011nnnndddd11110001mmmm") // v6
|
||||
INST(SHASX, "SHASX", "cccc01100011nnnndddd11110011mmmm") // v6
|
||||
INST(SHSAX, "SHSAX", "cccc01100011nnnndddd11110101mmmm") // v6
|
||||
INST(SHSUB8, "SHSUB8", "cccc01100011nnnndddd11111111mmmm") // v6
|
||||
INST(SHSUB16, "SHSUB16", "cccc01100011nnnndddd11110111mmmm") // v6
|
||||
INST(UHADD8, "UHADD8", "cccc01100111nnnndddd11111001mmmm") // v6
|
||||
INST(UHADD16, "UHADD16", "cccc01100111nnnndddd11110001mmmm") // v6
|
||||
INST(UHASX, "UHASX", "cccc01100111nnnndddd11110011mmmm") // v6
|
||||
INST(UHSAX, "UHSAX", "cccc01100111nnnndddd11110101mmmm") // v6
|
||||
INST(UHSUB8, "UHSUB8", "cccc01100111nnnndddd11111111mmmm") // v6
|
||||
INST(UHSUB16, "UHSUB16", "cccc01100111nnnndddd11110111mmmm") // v6
|
||||
|
||||
// Saturated Add/Subtract instructions
|
||||
INST(QADD, "QADD", "cccc00010000nnnndddd00000101mmmm") // v5xP
|
||||
INST(QSUB, "QSUB", "cccc00010010nnnndddd00000101mmmm") // v5xP
|
||||
INST(QDADD, "QDADD", "cccc00010100nnnndddd00000101mmmm") // v5xP
|
||||
INST(QDSUB, "QDSUB", "cccc00010110nnnndddd00000101mmmm") // v5xP
|
||||
|
||||
// Status Register Access instructions
|
||||
INST(CPS, "CPS", "111100010000---00000000---0-----") // v6
|
||||
INST(SETEND, "SETEND", "1111000100000001000000e000000000") // v6
|
||||
INST(MRS, "MRS", "cccc000100001111dddd000000000000") // v3
|
||||
INST(MSR_imm, "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv") // v3
|
||||
INST(MSR_reg, "MSR (reg)", "cccc00010010mmmm111100000000nnnn") // v3
|
||||
INST(RFE, "RFE", "1111100--0-1----0000101000000000") // v6
|
||||
INST(SRS, "SRS", "1111100--1-0110100000101000-----") // v6
|
||||
487
src/jit/frontend/decoder/arm32_table_generated.c
Normal file
487
src/jit/frontend/decoder/arm32_table_generated.c
Normal file
|
|
@ -0,0 +1,487 @@
|
|||
/* GENERATED FILE - DO NOT EDIT */
|
||||
#include "arm32.h"
|
||||
#include "arm32_table_generated.h"
|
||||
static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[261] = {
|
||||
{ "DMB", "1111010101111111111100000101oooo", 0xfffffff0U, 0xf57ff050U },
|
||||
{ "DSB", "1111010101111111111100000100oooo", 0xfffffff0U, 0xf57ff040U },
|
||||
{ "ISB", "1111010101111111111100000110oooo", 0xfffffff0U, 0xf57ff060U },
|
||||
{ "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv", 0xfe000000U, 0xfa000000U },
|
||||
{ "BLX (reg)", "cccc000100101111111111110011mmmm", 0x0ffffff0U, 0x012fff30U },
|
||||
{ "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0a000000U },
|
||||
{ "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0b000000U },
|
||||
{ "BX", "cccc000100101111111111110001mmmm", 0x0ffffff0U, 0x012fff10U },
|
||||
{ "BXJ", "cccc000100101111111111110010mmmm", 0x0ffffff0U, 0x012fff20U },
|
||||
{ "CRC32", "cccc00010zz0nnnndddd00000100mmmm", 0x0f900ff0U, 0x01000040U },
|
||||
{ "CRC32C", "cccc00010zz0nnnndddd00100100mmmm", 0x0f900ff0U, 0x01000240U },
|
||||
{ "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM", 0x0f000010U, 0x0e000000U },
|
||||
{ "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv", 0x0e100000U, 0x0c100000U },
|
||||
{ "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM", 0x0f100010U, 0x0e000010U },
|
||||
{ "MCRR", "cccc11000100uuuuttttppppooooMMMM", 0x0ff00000U, 0x0c400000U },
|
||||
{ "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM", 0x0f100010U, 0x0e100010U },
|
||||
{ "MRRC", "cccc11000101uuuuttttppppooooMMMM", 0x0ff00000U, 0x0c500000U },
|
||||
{ "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv", 0x0e100000U, 0x0c000000U },
|
||||
{ "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02a00000U },
|
||||
{ "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00a00000U },
|
||||
{ "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00a00010U },
|
||||
{ "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02800000U },
|
||||
{ "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00800000U },
|
||||
{ "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00800010U },
|
||||
{ "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02000000U },
|
||||
{ "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00000000U },
|
||||
{ "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00000010U },
|
||||
{ "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x03c00000U },
|
||||
{ "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x01c00000U },
|
||||
{ "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x01c00010U },
|
||||
{ "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03700000U },
|
||||
{ "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01700000U },
|
||||
{ "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01700010U },
|
||||
{ "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03500000U },
|
||||
{ "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01500000U },
|
||||
{ "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01500010U },
|
||||
{ "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02200000U },
|
||||
{ "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00200000U },
|
||||
{ "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00200010U },
|
||||
{ "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv", 0x0fef0000U, 0x03a00000U },
|
||||
{ "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm", 0x0fef0010U, 0x01a00000U },
|
||||
{ "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm", 0x0fef0090U, 0x01a00010U },
|
||||
{ "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv", 0x0fef0000U, 0x03e00000U },
|
||||
{ "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm", 0x0fef0010U, 0x01e00000U },
|
||||
{ "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm", 0x0fef0090U, 0x01e00010U },
|
||||
{ "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x03800000U },
|
||||
{ "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x01800000U },
|
||||
{ "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x01800010U },
|
||||
{ "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02600000U },
|
||||
{ "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00600000U },
|
||||
{ "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00600010U },
|
||||
{ "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02e00000U },
|
||||
{ "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00e00000U },
|
||||
{ "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00e00010U },
|
||||
{ "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02c00000U },
|
||||
{ "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00c00000U },
|
||||
{ "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00c00010U },
|
||||
{ "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02400000U },
|
||||
{ "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00400000U },
|
||||
{ "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00400010U },
|
||||
{ "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03300000U },
|
||||
{ "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01300000U },
|
||||
{ "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01300010U },
|
||||
{ "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03100000U },
|
||||
{ "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01100000U },
|
||||
{ "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01100010U },
|
||||
{ "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv", 0x0ff000f0U, 0x01200070U },
|
||||
{ "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0f000000U },
|
||||
{ "UDF", "111001111111------------1111----", 0xfff000f0U, 0xe7f000f0U },
|
||||
{ "SXTB", "cccc011010101111ddddrr000111mmmm", 0x0fff03f0U, 0x06af0070U },
|
||||
{ "SXTB16", "cccc011010001111ddddrr000111mmmm", 0x0fff03f0U, 0x068f0070U },
|
||||
{ "SXTH", "cccc011010111111ddddrr000111mmmm", 0x0fff03f0U, 0x06bf0070U },
|
||||
{ "SXTAB", "cccc01101010nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06a00070U },
|
||||
{ "SXTAB16", "cccc01101000nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06800070U },
|
||||
{ "SXTAH", "cccc01101011nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06b00070U },
|
||||
{ "UXTB", "cccc011011101111ddddrr000111mmmm", 0x0fff03f0U, 0x06ef0070U },
|
||||
{ "UXTB16", "cccc011011001111ddddrr000111mmmm", 0x0fff03f0U, 0x06cf0070U },
|
||||
{ "UXTH", "cccc011011111111ddddrr000111mmmm", 0x0fff03f0U, 0x06ff0070U },
|
||||
{ "UXTAB", "cccc01101110nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06e00070U },
|
||||
{ "UXTAB16", "cccc01101100nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06c00070U },
|
||||
{ "UXTAH", "cccc01101111nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06f00070U },
|
||||
{ "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii", 0xff30f000U, 0xf510f000U },
|
||||
{ "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm", 0xff30f010U, 0xf710f000U },
|
||||
{ "SEV", "----0011001000001111000000000100", 0x0fffffffU, 0x0320f004U },
|
||||
{ "SEVL", "----0011001000001111000000000101", 0x0fffffffU, 0x0320f005U },
|
||||
{ "WFE", "----0011001000001111000000000010", 0x0fffffffU, 0x0320f002U },
|
||||
{ "WFI", "----0011001000001111000000000011", 0x0fffffffU, 0x0320f003U },
|
||||
{ "YIELD", "----0011001000001111000000000001", 0x0fffffffU, 0x0320f001U },
|
||||
{ "Reserved Hint", "----0011001000001111------------", 0x0ffff000U, 0x0320f000U },
|
||||
{ "Reserved Hint", "----001100100000111100000000----", 0x0ffffff0U, 0x0320f000U },
|
||||
{ "CLREX", "11110101011111111111000000011111", 0xffffffffU, 0xf57ff01fU },
|
||||
{ "SWP", "cccc00010000nnnntttt00001001uuuu", 0x0ff00ff0U, 0x01000090U },
|
||||
{ "SWPB", "cccc00010100nnnntttt00001001uuuu", 0x0ff00ff0U, 0x01400090U },
|
||||
{ "STL", "cccc00011000nnnn111111001001tttt", 0x0ff0fff0U, 0x0180fc90U },
|
||||
{ "STLEX", "cccc00011000nnnndddd11101001tttt", 0x0ff00ff0U, 0x01800e90U },
|
||||
{ "STREX", "cccc00011000nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01800f90U },
|
||||
{ "LDA", "cccc00011001nnnndddd110010011111", 0x0ff00fffU, 0x01900c9fU },
|
||||
{ "LDAEX", "cccc00011001nnnndddd111010011111", 0x0ff00fffU, 0x01900e9fU },
|
||||
{ "LDREX", "cccc00011001nnnndddd111110011111", 0x0ff00fffU, 0x01900f9fU },
|
||||
{ "STLEXD", "cccc00011010nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01a00e90U },
|
||||
{ "STREXD", "cccc00011010nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01a00f90U },
|
||||
{ "LDAEXD", "cccc00011011nnnndddd111010011111", 0x0ff00fffU, 0x01b00e9fU },
|
||||
{ "LDREXD", "cccc00011011nnnndddd111110011111", 0x0ff00fffU, 0x01b00f9fU },
|
||||
{ "STLB", "cccc00011100nnnn111111001001tttt", 0x0ff0fff0U, 0x01c0fc90U },
|
||||
{ "STLEXB", "cccc00011100nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01c00e90U },
|
||||
{ "STREXB", "cccc00011100nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01c00f90U },
|
||||
{ "LDAB", "cccc00011101nnnndddd110010011111", 0x0ff00fffU, 0x01d00c9fU },
|
||||
{ "LDAEXB", "cccc00011101nnnndddd111010011111", 0x0ff00fffU, 0x01d00e9fU },
|
||||
{ "LDREXB", "cccc00011101nnnndddd111110011111", 0x0ff00fffU, 0x01d00f9fU },
|
||||
{ "STLH", "cccc00011110nnnn111111001001mmmm", 0x0ff0fff0U, 0x01e0fc90U },
|
||||
{ "STLEXH", "cccc00011110nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01e00e90U },
|
||||
{ "STREXH", "cccc00011110nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01e00f90U },
|
||||
{ "LDAH", "cccc00011111nnnndddd110010011111", 0x0ff00fffU, 0x01f00c9fU },
|
||||
{ "LDAEXH", "cccc00011111nnnndddd111010011111", 0x0ff00fffU, 0x01f00e9fU },
|
||||
{ "LDREXH", "cccc00011111nnnndddd111110011111", 0x0ff00fffU, 0x01f00f9fU },
|
||||
{ "LDRBT (A1)", "----0100-111--------------------", 0x0f700000U, 0x04700000U },
|
||||
{ "LDRBT (A2)", "----0110-111---------------0----", 0x0f700010U, 0x06700000U },
|
||||
{ "LDRHT (A1)", "----0000-111------------1011----", 0x0f7000f0U, 0x007000b0U },
|
||||
{ "LDRHT (A1)", "----0000-1111111--------1011----", 0x0f7f00f0U, 0x007f00b0U },
|
||||
{ "LDRHT (A2)", "----0000-011--------00001011----", 0x0f700ff0U, 0x003000b0U },
|
||||
{ "LDRSBT (A1)", "----0000-111------------1101----", 0x0f7000f0U, 0x007000d0U },
|
||||
{ "LDRSBT (A2)", "----0000-011--------00001101----", 0x0f700ff0U, 0x003000d0U },
|
||||
{ "LDRSHT (A1)", "----0000-111------------1111----", 0x0f7000f0U, 0x007000f0U },
|
||||
{ "LDRSHT (A2)", "----0000-011--------00001111----", 0x0f700ff0U, 0x003000f0U },
|
||||
{ "LDRT (A1)", "----0100-011--------------------", 0x0f700000U, 0x04300000U },
|
||||
{ "LDRT (A2)", "----0110-011---------------0----", 0x0f700010U, 0x06300000U },
|
||||
{ "STRBT (A1)", "----0100-110--------------------", 0x0f700000U, 0x04600000U },
|
||||
{ "STRBT (A2)", "----0110-110---------------0----", 0x0f700010U, 0x06600000U },
|
||||
{ "STRHT (A1)", "----0000-110------------1011----", 0x0f7000f0U, 0x006000b0U },
|
||||
{ "STRHT (A2)", "----0000-010--------00001011----", 0x0f700ff0U, 0x002000b0U },
|
||||
{ "STRT (A1)", "----0100-010--------------------", 0x0f700000U, 0x04200000U },
|
||||
{ "STRT (A2)", "----0110-010---------------0----", 0x0f700010U, 0x06200000U },
|
||||
{ "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv", 0x0f7f0000U, 0x051f0000U },
|
||||
{ "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04100000U },
|
||||
{ "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06100000U },
|
||||
{ "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv", 0x0f7f0000U, 0x055f0000U },
|
||||
{ "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04500000U },
|
||||
{ "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06500000U },
|
||||
{ "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv", 0x0f7f00f0U, 0x014f00d0U },
|
||||
{ "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv", 0x0e5000f0U, 0x004000d0U },
|
||||
{ "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm", 0x0e500ff0U, 0x000000d0U },
|
||||
{ "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv", 0x0e5f00f0U, 0x005f00b0U },
|
||||
{ "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv", 0x0e5000f0U, 0x005000b0U },
|
||||
{ "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm", 0x0e500ff0U, 0x001000b0U },
|
||||
{ "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv", 0x0f7f00f0U, 0x015f00d0U },
|
||||
{ "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv", 0x0e5000f0U, 0x005000d0U },
|
||||
{ "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm", 0x0e500ff0U, 0x001000d0U },
|
||||
{ "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv", 0x0f7f00f0U, 0x015f00f0U },
|
||||
{ "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv", 0x0e5000f0U, 0x005000f0U },
|
||||
{ "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm", 0x0e500ff0U, 0x001000f0U },
|
||||
{ "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04000000U },
|
||||
{ "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06000000U },
|
||||
{ "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04400000U },
|
||||
{ "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06400000U },
|
||||
{ "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv", 0x0e5000f0U, 0x004000f0U },
|
||||
{ "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm", 0x0e500ff0U, 0x000000f0U },
|
||||
{ "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv", 0x0e5000f0U, 0x004000b0U },
|
||||
{ "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm", 0x0e500ff0U, 0x000000b0U },
|
||||
{ "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08900000U },
|
||||
{ "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08100000U },
|
||||
{ "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09100000U },
|
||||
{ "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09900000U },
|
||||
{ "LDM (usr reg)", "----100--101--------------------", 0x0e700000U, 0x08500000U },
|
||||
{ "LDM (exce ret)", "----100--1-1----1---------------", 0x0e508000U, 0x08508000U },
|
||||
{ "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08800000U },
|
||||
{ "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08000000U },
|
||||
{ "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09000000U },
|
||||
{ "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09800000U },
|
||||
{ "STM (usr reg)", "----100--100--------------------", 0x0e700000U, 0x08400000U },
|
||||
{ "BFC", "cccc0111110vvvvvddddvvvvv0011111", 0x0fe0007fU, 0x07c0001fU },
|
||||
{ "BFI", "cccc0111110vvvvvddddvvvvv001nnnn", 0x0fe00070U, 0x07c00010U },
|
||||
{ "CLZ", "cccc000101101111dddd11110001mmmm", 0x0fff0ff0U, 0x016f0f10U },
|
||||
{ "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv", 0x0ff00000U, 0x03400000U },
|
||||
{ "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv", 0x0ff00000U, 0x03000000U },
|
||||
{ "NOP", "----0011001000001111000000000000", 0x0fffffffU, 0x0320f000U },
|
||||
{ "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn", 0x0fe00070U, 0x07a00050U },
|
||||
{ "SEL", "cccc01101000nnnndddd11111011mmmm", 0x0ff00ff0U, 0x06800fb0U },
|
||||
{ "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn", 0x0fe00070U, 0x07e00050U },
|
||||
{ "USAD8", "cccc01111000dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0780f010U },
|
||||
{ "USADA8", "cccc01111000ddddaaaammmm0001nnnn", 0x0ff000f0U, 0x07800010U },
|
||||
{ "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm", 0x0ff00070U, 0x06800010U },
|
||||
{ "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm", 0x0ff00070U, 0x06800050U },
|
||||
{ "RBIT", "cccc011011111111dddd11110011mmmm", 0x0fff0ff0U, 0x06ff0f30U },
|
||||
{ "REV", "cccc011010111111dddd11110011mmmm", 0x0fff0ff0U, 0x06bf0f30U },
|
||||
{ "REV16", "cccc011010111111dddd11111011mmmm", 0x0fff0ff0U, 0x06bf0fb0U },
|
||||
{ "REVSH", "cccc011011111111dddd11111011mmmm", 0x0fff0ff0U, 0x06ff0fb0U },
|
||||
{ "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn", 0x0fe00030U, 0x06a00010U },
|
||||
{ "SSAT16", "cccc01101010vvvvdddd11110011nnnn", 0x0ff00ff0U, 0x06a00f30U },
|
||||
{ "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn", 0x0fe00030U, 0x06e00010U },
|
||||
{ "USAT16", "cccc01101110vvvvdddd11110011nnnn", 0x0ff00ff0U, 0x06e00f30U },
|
||||
{ "SDIV", "cccc01110001dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0710f010U },
|
||||
{ "UDIV", "cccc01110011dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0730f010U },
|
||||
{ "MLA", "cccc0000001Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00200090U },
|
||||
{ "MLS", "cccc00000110ddddaaaammmm1001nnnn", 0x0ff000f0U, 0x00600090U },
|
||||
{ "MUL", "cccc0000000Sdddd0000mmmm1001nnnn", 0x0fe0f0f0U, 0x00000090U },
|
||||
{ "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00e00090U },
|
||||
{ "SMULL", "cccc0000110Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00c00090U },
|
||||
{ "UMAAL", "cccc00000100ddddaaaammmm1001nnnn", 0x0ff000f0U, 0x00400090U },
|
||||
{ "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00a00090U },
|
||||
{ "UMULL", "cccc0000100Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00800090U },
|
||||
{ "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn", 0x0ff00090U, 0x01400080U },
|
||||
{ "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn", 0x0ff00090U, 0x01000080U },
|
||||
{ "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn", 0x0ff0f090U, 0x01600080U },
|
||||
{ "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn", 0x0ff000b0U, 0x01200080U },
|
||||
{ "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn", 0x0ff0f0b0U, 0x012000a0U },
|
||||
{ "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn", 0x0ff0f0d0U, 0x0750f010U },
|
||||
{ "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn", 0x0ff000d0U, 0x07500010U },
|
||||
{ "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn", 0x0ff000d0U, 0x075000d0U },
|
||||
{ "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn", 0x0ff000d0U, 0x07000010U },
|
||||
{ "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn", 0x0ff000d0U, 0x07400010U },
|
||||
{ "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn", 0x0ff000d0U, 0x07000050U },
|
||||
{ "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn", 0x0ff000d0U, 0x07400050U },
|
||||
{ "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn", 0x0ff0f0d0U, 0x0700f010U },
|
||||
{ "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn", 0x0ff0f0d0U, 0x0700f050U },
|
||||
{ "SADD8", "cccc01100001nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06100f90U },
|
||||
{ "SADD16", "cccc01100001nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06100f10U },
|
||||
{ "SASX", "cccc01100001nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06100f30U },
|
||||
{ "SSAX", "cccc01100001nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06100f50U },
|
||||
{ "SSUB8", "cccc01100001nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06100ff0U },
|
||||
{ "SSUB16", "cccc01100001nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06100f70U },
|
||||
{ "UADD8", "cccc01100101nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06500f90U },
|
||||
{ "UADD16", "cccc01100101nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06500f10U },
|
||||
{ "UASX", "cccc01100101nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06500f30U },
|
||||
{ "USAX", "cccc01100101nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06500f50U },
|
||||
{ "USUB8", "cccc01100101nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06500ff0U },
|
||||
{ "USUB16", "cccc01100101nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06500f70U },
|
||||
{ "QADD8", "cccc01100010nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06200f90U },
|
||||
{ "QADD16", "cccc01100010nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06200f10U },
|
||||
{ "QASX", "cccc01100010nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06200f30U },
|
||||
{ "QSAX", "cccc01100010nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06200f50U },
|
||||
{ "QSUB8", "cccc01100010nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06200ff0U },
|
||||
{ "QSUB16", "cccc01100010nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06200f70U },
|
||||
{ "UQADD8", "cccc01100110nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06600f90U },
|
||||
{ "UQADD16", "cccc01100110nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06600f10U },
|
||||
{ "UQASX", "cccc01100110nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06600f30U },
|
||||
{ "UQSAX", "cccc01100110nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06600f50U },
|
||||
{ "UQSUB8", "cccc01100110nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06600ff0U },
|
||||
{ "UQSUB16", "cccc01100110nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06600f70U },
|
||||
{ "SHADD8", "cccc01100011nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06300f90U },
|
||||
{ "SHADD16", "cccc01100011nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06300f10U },
|
||||
{ "SHASX", "cccc01100011nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06300f30U },
|
||||
{ "SHSAX", "cccc01100011nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06300f50U },
|
||||
{ "SHSUB8", "cccc01100011nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06300ff0U },
|
||||
{ "SHSUB16", "cccc01100011nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06300f70U },
|
||||
{ "UHADD8", "cccc01100111nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06700f90U },
|
||||
{ "UHADD16", "cccc01100111nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06700f10U },
|
||||
{ "UHASX", "cccc01100111nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06700f30U },
|
||||
{ "UHSAX", "cccc01100111nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06700f50U },
|
||||
{ "UHSUB8", "cccc01100111nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06700ff0U },
|
||||
{ "UHSUB16", "cccc01100111nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06700f70U },
|
||||
{ "QADD", "cccc00010000nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01000050U },
|
||||
{ "QSUB", "cccc00010010nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01200050U },
|
||||
{ "QDADD", "cccc00010100nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01400050U },
|
||||
{ "QDSUB", "cccc00010110nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01600050U },
|
||||
{ "CPS", "111100010000---00000000---0-----", 0xfff1fe20U, 0xf1000000U },
|
||||
{ "SETEND", "1111000100000001000000e000000000", 0xfffffdffU, 0xf1010000U },
|
||||
{ "MRS", "cccc000100001111dddd000000000000", 0x0fff0fffU, 0x010f0000U },
|
||||
{ "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv", 0x0ff0f000U, 0x0320f000U },
|
||||
{ "MSR (reg)", "cccc00010010mmmm111100000000nnnn", 0x0ff0fff0U, 0x0120f000U },
|
||||
{ "RFE", "1111100--0-1----0000101000000000", 0xfe50ffffU, 0xf8100a00U },
|
||||
{ "SRS", "1111100--1-0110100000101000-----", 0xfe5fffe0U, 0xf84d0500U },
|
||||
};
|
||||
|
||||
const decode_bucket_t g_decoder_lookup_table[4096] = {
|
||||
[0x000] = { .instructions = { &g_instructions[25], }, .count = 1U },
|
||||
[0x001] = { .instructions = { &g_instructions[26], }, .count = 1U },
|
||||
[0x009] = { .instructions = { &g_instructions[194], }, .count = 1U },
|
||||
[0x00b] = { .instructions = { &g_instructions[157], }, .count = 1U },
|
||||
[0x00d] = { .instructions = { &g_instructions[140], }, .count = 1U },
|
||||
[0x00f] = { .instructions = { &g_instructions[155], }, .count = 1U },
|
||||
[0x01b] = { .instructions = { &g_instructions[143], }, .count = 1U },
|
||||
[0x01d] = { .instructions = { &g_instructions[146], }, .count = 1U },
|
||||
[0x01f] = { .instructions = { &g_instructions[149], }, .count = 1U },
|
||||
[0x020] = { .instructions = { &g_instructions[37], }, .count = 1U },
|
||||
[0x021] = { .instructions = { &g_instructions[38], }, .count = 1U },
|
||||
[0x029] = { .instructions = { &g_instructions[192], }, .count = 1U },
|
||||
[0x02b] = { .instructions = { &g_instructions[129], }, .count = 1U },
|
||||
[0x03b] = { .instructions = { &g_instructions[119], }, .count = 1U },
|
||||
[0x03d] = { .instructions = { &g_instructions[121], }, .count = 1U },
|
||||
[0x03f] = { .instructions = { &g_instructions[123], }, .count = 1U },
|
||||
[0x040] = { .instructions = { &g_instructions[58], }, .count = 1U },
|
||||
[0x041] = { .instructions = { &g_instructions[59], }, .count = 1U },
|
||||
[0x049] = { .instructions = { &g_instructions[197], }, .count = 1U },
|
||||
[0x04b] = { .instructions = { &g_instructions[156], }, .count = 1U },
|
||||
[0x04d] = { .instructions = { &g_instructions[139], }, .count = 1U },
|
||||
[0x04f] = { .instructions = { &g_instructions[154], }, .count = 1U },
|
||||
[0x05b] = { .instructions = { &g_instructions[141], &g_instructions[142], }, .count = 2U },
|
||||
[0x05d] = { .instructions = { &g_instructions[145], }, .count = 1U },
|
||||
[0x05f] = { .instructions = { &g_instructions[148], }, .count = 1U },
|
||||
[0x060] = { .instructions = { &g_instructions[49], }, .count = 1U },
|
||||
[0x061] = { .instructions = { &g_instructions[50], }, .count = 1U },
|
||||
[0x069] = { .instructions = { &g_instructions[193], }, .count = 1U },
|
||||
[0x06b] = { .instructions = { &g_instructions[128], }, .count = 1U },
|
||||
[0x07b] = { .instructions = { &g_instructions[117], &g_instructions[118], }, .count = 2U },
|
||||
[0x07d] = { .instructions = { &g_instructions[120], }, .count = 1U },
|
||||
[0x07f] = { .instructions = { &g_instructions[122], }, .count = 1U },
|
||||
[0x080] = { .instructions = { &g_instructions[22], }, .count = 1U },
|
||||
[0x081] = { .instructions = { &g_instructions[23], }, .count = 1U },
|
||||
[0x089] = { .instructions = { &g_instructions[199], }, .count = 1U },
|
||||
[0x0a0] = { .instructions = { &g_instructions[19], }, .count = 1U },
|
||||
[0x0a1] = { .instructions = { &g_instructions[20], }, .count = 1U },
|
||||
[0x0a9] = { .instructions = { &g_instructions[198], }, .count = 1U },
|
||||
[0x0c0] = { .instructions = { &g_instructions[55], }, .count = 1U },
|
||||
[0x0c1] = { .instructions = { &g_instructions[56], }, .count = 1U },
|
||||
[0x0c9] = { .instructions = { &g_instructions[196], }, .count = 1U },
|
||||
[0x0e0] = { .instructions = { &g_instructions[52], }, .count = 1U },
|
||||
[0x0e1] = { .instructions = { &g_instructions[53], }, .count = 1U },
|
||||
[0x0e9] = { .instructions = { &g_instructions[195], }, .count = 1U },
|
||||
[0x100] = { .instructions = { &g_instructions[254], &g_instructions[255], &g_instructions[256], }, .count = 3U },
|
||||
[0x104] = { .instructions = { &g_instructions[9], &g_instructions[10], }, .count = 2U },
|
||||
[0x105] = { .instructions = { &g_instructions[250], }, .count = 1U },
|
||||
[0x108] = { .instructions = { &g_instructions[201], }, .count = 1U },
|
||||
[0x109] = { .instructions = { &g_instructions[91], }, .count = 1U },
|
||||
[0x110] = { .instructions = { &g_instructions[64], }, .count = 1U },
|
||||
[0x111] = { .instructions = { &g_instructions[65], }, .count = 1U },
|
||||
[0x120] = { .instructions = { &g_instructions[258], }, .count = 1U },
|
||||
[0x121] = { .instructions = { &g_instructions[7], }, .count = 1U },
|
||||
[0x122] = { .instructions = { &g_instructions[8], }, .count = 1U },
|
||||
[0x123] = { .instructions = { &g_instructions[4], }, .count = 1U },
|
||||
[0x125] = { .instructions = { &g_instructions[251], }, .count = 1U },
|
||||
[0x127] = { .instructions = { &g_instructions[66], }, .count = 1U },
|
||||
[0x128] = { .instructions = { &g_instructions[203], }, .count = 1U },
|
||||
[0x12a] = { .instructions = { &g_instructions[204], }, .count = 1U },
|
||||
[0x130] = { .instructions = { &g_instructions[61], }, .count = 1U },
|
||||
[0x131] = { .instructions = { &g_instructions[62], }, .count = 1U },
|
||||
[0x145] = { .instructions = { &g_instructions[252], }, .count = 1U },
|
||||
[0x148] = { .instructions = { &g_instructions[200], }, .count = 1U },
|
||||
[0x149] = { .instructions = { &g_instructions[92], }, .count = 1U },
|
||||
[0x14d] = { .instructions = { &g_instructions[138], }, .count = 1U },
|
||||
[0x150] = { .instructions = { &g_instructions[34], }, .count = 1U },
|
||||
[0x151] = { .instructions = { &g_instructions[35], }, .count = 1U },
|
||||
[0x15d] = { .instructions = { &g_instructions[144], }, .count = 1U },
|
||||
[0x15f] = { .instructions = { &g_instructions[147], }, .count = 1U },
|
||||
[0x161] = { .instructions = { &g_instructions[171], }, .count = 1U },
|
||||
[0x165] = { .instructions = { &g_instructions[253], }, .count = 1U },
|
||||
[0x168] = { .instructions = { &g_instructions[202], }, .count = 1U },
|
||||
[0x170] = { .instructions = { &g_instructions[31], }, .count = 1U },
|
||||
[0x171] = { .instructions = { &g_instructions[32], }, .count = 1U },
|
||||
[0x180] = { .instructions = { &g_instructions[46], }, .count = 1U },
|
||||
[0x181] = { .instructions = { &g_instructions[47], }, .count = 1U },
|
||||
[0x189] = { .instructions = { &g_instructions[93], &g_instructions[94], &g_instructions[95], }, .count = 3U },
|
||||
[0x199] = { .instructions = { &g_instructions[96], &g_instructions[97], &g_instructions[98], }, .count = 3U },
|
||||
[0x1a0] = { .instructions = { &g_instructions[40], }, .count = 1U },
|
||||
[0x1a1] = { .instructions = { &g_instructions[41], }, .count = 1U },
|
||||
[0x1a9] = { .instructions = { &g_instructions[99], &g_instructions[100], }, .count = 2U },
|
||||
[0x1b9] = { .instructions = { &g_instructions[101], &g_instructions[102], }, .count = 2U },
|
||||
[0x1c0] = { .instructions = { &g_instructions[28], }, .count = 1U },
|
||||
[0x1c1] = { .instructions = { &g_instructions[29], }, .count = 1U },
|
||||
[0x1c9] = { .instructions = { &g_instructions[103], &g_instructions[104], &g_instructions[105], }, .count = 3U },
|
||||
[0x1d9] = { .instructions = { &g_instructions[106], &g_instructions[107], &g_instructions[108], }, .count = 3U },
|
||||
[0x1e0] = { .instructions = { &g_instructions[43], }, .count = 1U },
|
||||
[0x1e1] = { .instructions = { &g_instructions[44], }, .count = 1U },
|
||||
[0x1e9] = { .instructions = { &g_instructions[109], &g_instructions[110], &g_instructions[111], }, .count = 3U },
|
||||
[0x1f9] = { .instructions = { &g_instructions[112], &g_instructions[113], &g_instructions[114], }, .count = 3U },
|
||||
[0x200] = { .instructions = { &g_instructions[24], }, .count = 1U },
|
||||
[0x220] = { .instructions = { &g_instructions[36], }, .count = 1U },
|
||||
[0x240] = { .instructions = { &g_instructions[57], }, .count = 1U },
|
||||
[0x260] = { .instructions = { &g_instructions[48], }, .count = 1U },
|
||||
[0x280] = { .instructions = { &g_instructions[21], }, .count = 1U },
|
||||
[0x2a0] = { .instructions = { &g_instructions[18], }, .count = 1U },
|
||||
[0x2c0] = { .instructions = { &g_instructions[54], }, .count = 1U },
|
||||
[0x2e0] = { .instructions = { &g_instructions[51], }, .count = 1U },
|
||||
[0x300] = { .instructions = { &g_instructions[173], }, .count = 1U },
|
||||
[0x310] = { .instructions = { &g_instructions[63], }, .count = 1U },
|
||||
[0x320] = { .instructions = { &g_instructions[83], &g_instructions[84], &g_instructions[85], &g_instructions[86], &g_instructions[87], &g_instructions[88], &g_instructions[89], &g_instructions[174], &g_instructions[257], }, .count = 9U },
|
||||
[0x330] = { .instructions = { &g_instructions[60], }, .count = 1U },
|
||||
[0x340] = { .instructions = { &g_instructions[172], }, .count = 1U },
|
||||
[0x350] = { .instructions = { &g_instructions[33], }, .count = 1U },
|
||||
[0x370] = { .instructions = { &g_instructions[30], }, .count = 1U },
|
||||
[0x380] = { .instructions = { &g_instructions[45], }, .count = 1U },
|
||||
[0x3a0] = { .instructions = { &g_instructions[39], }, .count = 1U },
|
||||
[0x3c0] = { .instructions = { &g_instructions[27], }, .count = 1U },
|
||||
[0x3e0] = { .instructions = { &g_instructions[42], }, .count = 1U },
|
||||
[0x400] = { .instructions = { &g_instructions[150], }, .count = 1U },
|
||||
[0x410] = { .instructions = { &g_instructions[133], }, .count = 1U },
|
||||
[0x420] = { .instructions = { &g_instructions[130], }, .count = 1U },
|
||||
[0x430] = { .instructions = { &g_instructions[124], }, .count = 1U },
|
||||
[0x440] = { .instructions = { &g_instructions[152], }, .count = 1U },
|
||||
[0x450] = { .instructions = { &g_instructions[136], }, .count = 1U },
|
||||
[0x460] = { .instructions = { &g_instructions[126], }, .count = 1U },
|
||||
[0x470] = { .instructions = { &g_instructions[115], }, .count = 1U },
|
||||
[0x510] = { .instructions = { &g_instructions[81], &g_instructions[132], }, .count = 2U },
|
||||
[0x550] = { .instructions = { &g_instructions[135], }, .count = 1U },
|
||||
[0x571] = { .instructions = { &g_instructions[90], }, .count = 1U },
|
||||
[0x574] = { .instructions = { &g_instructions[1], }, .count = 1U },
|
||||
[0x575] = { .instructions = { &g_instructions[0], }, .count = 1U },
|
||||
[0x576] = { .instructions = { &g_instructions[2], }, .count = 1U },
|
||||
[0x600] = { .instructions = { &g_instructions[151], }, .count = 1U },
|
||||
[0x610] = { .instructions = { &g_instructions[134], }, .count = 1U },
|
||||
[0x611] = { .instructions = { &g_instructions[215], }, .count = 1U },
|
||||
[0x613] = { .instructions = { &g_instructions[216], }, .count = 1U },
|
||||
[0x615] = { .instructions = { &g_instructions[217], }, .count = 1U },
|
||||
[0x617] = { .instructions = { &g_instructions[219], }, .count = 1U },
|
||||
[0x619] = { .instructions = { &g_instructions[214], }, .count = 1U },
|
||||
[0x61f] = { .instructions = { &g_instructions[218], }, .count = 1U },
|
||||
[0x620] = { .instructions = { &g_instructions[131], }, .count = 1U },
|
||||
[0x621] = { .instructions = { &g_instructions[227], }, .count = 1U },
|
||||
[0x623] = { .instructions = { &g_instructions[228], }, .count = 1U },
|
||||
[0x625] = { .instructions = { &g_instructions[229], }, .count = 1U },
|
||||
[0x627] = { .instructions = { &g_instructions[231], }, .count = 1U },
|
||||
[0x629] = { .instructions = { &g_instructions[226], }, .count = 1U },
|
||||
[0x62f] = { .instructions = { &g_instructions[230], }, .count = 1U },
|
||||
[0x630] = { .instructions = { &g_instructions[125], }, .count = 1U },
|
||||
[0x631] = { .instructions = { &g_instructions[239], }, .count = 1U },
|
||||
[0x633] = { .instructions = { &g_instructions[240], }, .count = 1U },
|
||||
[0x635] = { .instructions = { &g_instructions[241], }, .count = 1U },
|
||||
[0x637] = { .instructions = { &g_instructions[243], }, .count = 1U },
|
||||
[0x639] = { .instructions = { &g_instructions[238], }, .count = 1U },
|
||||
[0x63f] = { .instructions = { &g_instructions[242], }, .count = 1U },
|
||||
[0x640] = { .instructions = { &g_instructions[153], }, .count = 1U },
|
||||
[0x650] = { .instructions = { &g_instructions[137], }, .count = 1U },
|
||||
[0x651] = { .instructions = { &g_instructions[221], }, .count = 1U },
|
||||
[0x653] = { .instructions = { &g_instructions[222], }, .count = 1U },
|
||||
[0x655] = { .instructions = { &g_instructions[223], }, .count = 1U },
|
||||
[0x657] = { .instructions = { &g_instructions[225], }, .count = 1U },
|
||||
[0x659] = { .instructions = { &g_instructions[220], }, .count = 1U },
|
||||
[0x65f] = { .instructions = { &g_instructions[224], }, .count = 1U },
|
||||
[0x660] = { .instructions = { &g_instructions[127], }, .count = 1U },
|
||||
[0x661] = { .instructions = { &g_instructions[233], }, .count = 1U },
|
||||
[0x663] = { .instructions = { &g_instructions[234], }, .count = 1U },
|
||||
[0x665] = { .instructions = { &g_instructions[235], }, .count = 1U },
|
||||
[0x667] = { .instructions = { &g_instructions[237], }, .count = 1U },
|
||||
[0x669] = { .instructions = { &g_instructions[232], }, .count = 1U },
|
||||
[0x66f] = { .instructions = { &g_instructions[236], }, .count = 1U },
|
||||
[0x670] = { .instructions = { &g_instructions[116], }, .count = 1U },
|
||||
[0x671] = { .instructions = { &g_instructions[245], }, .count = 1U },
|
||||
[0x673] = { .instructions = { &g_instructions[246], }, .count = 1U },
|
||||
[0x675] = { .instructions = { &g_instructions[247], }, .count = 1U },
|
||||
[0x677] = { .instructions = { &g_instructions[249], }, .count = 1U },
|
||||
[0x679] = { .instructions = { &g_instructions[244], }, .count = 1U },
|
||||
[0x67f] = { .instructions = { &g_instructions[248], }, .count = 1U },
|
||||
[0x681] = { .instructions = { &g_instructions[180], }, .count = 1U },
|
||||
[0x685] = { .instructions = { &g_instructions[181], }, .count = 1U },
|
||||
[0x687] = { .instructions = { &g_instructions[70], &g_instructions[73], }, .count = 2U },
|
||||
[0x68b] = { .instructions = { &g_instructions[176], }, .count = 1U },
|
||||
[0x6a1] = { .instructions = { &g_instructions[186], }, .count = 1U },
|
||||
[0x6a3] = { .instructions = { &g_instructions[187], }, .count = 1U },
|
||||
[0x6a7] = { .instructions = { &g_instructions[69], &g_instructions[72], }, .count = 2U },
|
||||
[0x6b3] = { .instructions = { &g_instructions[183], }, .count = 1U },
|
||||
[0x6b7] = { .instructions = { &g_instructions[71], &g_instructions[74], }, .count = 2U },
|
||||
[0x6bb] = { .instructions = { &g_instructions[184], }, .count = 1U },
|
||||
[0x6c7] = { .instructions = { &g_instructions[76], &g_instructions[79], }, .count = 2U },
|
||||
[0x6e1] = { .instructions = { &g_instructions[188], }, .count = 1U },
|
||||
[0x6e3] = { .instructions = { &g_instructions[189], }, .count = 1U },
|
||||
[0x6e7] = { .instructions = { &g_instructions[75], &g_instructions[78], }, .count = 2U },
|
||||
[0x6f3] = { .instructions = { &g_instructions[182], }, .count = 1U },
|
||||
[0x6f7] = { .instructions = { &g_instructions[77], &g_instructions[80], }, .count = 2U },
|
||||
[0x6fb] = { .instructions = { &g_instructions[185], }, .count = 1U },
|
||||
[0x701] = { .instructions = { &g_instructions[208], &g_instructions[212], }, .count = 2U },
|
||||
[0x705] = { .instructions = { &g_instructions[210], &g_instructions[213], }, .count = 2U },
|
||||
[0x710] = { .instructions = { &g_instructions[82], }, .count = 1U },
|
||||
[0x711] = { .instructions = { &g_instructions[190], }, .count = 1U },
|
||||
[0x731] = { .instructions = { &g_instructions[191], }, .count = 1U },
|
||||
[0x741] = { .instructions = { &g_instructions[209], }, .count = 1U },
|
||||
[0x745] = { .instructions = { &g_instructions[211], }, .count = 1U },
|
||||
[0x751] = { .instructions = { &g_instructions[205], &g_instructions[206], }, .count = 2U },
|
||||
[0x75d] = { .instructions = { &g_instructions[207], }, .count = 1U },
|
||||
[0x781] = { .instructions = { &g_instructions[178], &g_instructions[179], }, .count = 2U },
|
||||
[0x7a5] = { .instructions = { &g_instructions[175], }, .count = 1U },
|
||||
[0x7c1] = { .instructions = { &g_instructions[169], &g_instructions[170], }, .count = 2U },
|
||||
[0x7e5] = { .instructions = { &g_instructions[177], }, .count = 1U },
|
||||
[0x7ff] = { .instructions = { &g_instructions[68], }, .count = 1U },
|
||||
[0x800] = { .instructions = { &g_instructions[165], }, .count = 1U },
|
||||
[0x810] = { .instructions = { &g_instructions[159], &g_instructions[259], }, .count = 2U },
|
||||
[0x840] = { .instructions = { &g_instructions[168], &g_instructions[260], }, .count = 2U },
|
||||
[0x850] = { .instructions = { &g_instructions[162], &g_instructions[163], }, .count = 2U },
|
||||
[0x880] = { .instructions = { &g_instructions[164], }, .count = 1U },
|
||||
[0x890] = { .instructions = { &g_instructions[158], }, .count = 1U },
|
||||
[0x900] = { .instructions = { &g_instructions[166], }, .count = 1U },
|
||||
[0x910] = { .instructions = { &g_instructions[160], }, .count = 1U },
|
||||
[0x980] = { .instructions = { &g_instructions[167], }, .count = 1U },
|
||||
[0x990] = { .instructions = { &g_instructions[161], }, .count = 1U },
|
||||
[0xa00] = { .instructions = { &g_instructions[3], &g_instructions[5], }, .count = 2U },
|
||||
[0xb00] = { .instructions = { &g_instructions[6], }, .count = 1U },
|
||||
[0xc00] = { .instructions = { &g_instructions[17], }, .count = 1U },
|
||||
[0xc10] = { .instructions = { &g_instructions[12], }, .count = 1U },
|
||||
[0xc40] = { .instructions = { &g_instructions[14], }, .count = 1U },
|
||||
[0xc50] = { .instructions = { &g_instructions[16], }, .count = 1U },
|
||||
[0xe00] = { .instructions = { &g_instructions[11], }, .count = 1U },
|
||||
[0xe01] = { .instructions = { &g_instructions[13], }, .count = 1U },
|
||||
[0xe11] = { .instructions = { &g_instructions[15], }, .count = 1U },
|
||||
[0xf00] = { .instructions = { &g_instructions[67], }, .count = 1U },
|
||||
};
|
||||
16
src/jit/frontend/decoder/arm32_table_generated.h
Normal file
16
src/jit/frontend/decoder/arm32_table_generated.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef POUND_JIT_DECODER_ARM32_GENERATED_H
|
||||
#define POUND_JIT_DECODER_ARM32_GENERATED_H
|
||||
|
||||
#include "arm32.h"
|
||||
#include <stddef.h>
|
||||
|
||||
#define LOOKUP_TABLE_MAX_BUCKET_SIZE 18U
|
||||
|
||||
typedef struct {
|
||||
const pvm_jit_decoder_arm32_instruction_info_t *instructions[LOOKUP_TABLE_MAX_BUCKET_SIZE];
|
||||
size_t count;
|
||||
} decode_bucket_t;
|
||||
|
||||
extern const decode_bucket_t g_decoder_lookup_table[4096];
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue