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aarch64: Correct vCPU register state and add FP/SIMD support

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The initial vCPU state for AArch64 had a couple of architectural
inaccuracies that this commit corrects.

First, AArch64 has 32 general-purpose registers (X0-X31), not 31.
The stack pointer (SP) is not a separate special-purpose register
but is an alias for register X31. The dedicated `sp` field in
vcpu_state_t was therefore redundant and architecturally incorrect.
This change increases GP_REGISTERS to 32 and removes the separate
`sp` field. The SP should be managed via `r[31]`.

Second, to support floating-point and SIMD instructions, the vCPU
state must include the vector registers. This adds the definitions
and storage for the 32 128-bit FP/SIMD registers (V0-V31).

Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar 2025-08-12 06:05:31 -04:00
parent 4456e23f7c
commit f15417802d
1 changed files with 9 additions and 5 deletions
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14
core/aarch64/isa.h
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@ -9,16 +9,20 @@
namespace aarch64
{
/* AArch64 R0-R30 */
#define GP_REGISTERS 31
/* AArch64 R0-R31 */
#define GP_REGISTERS 32
/* AArch64 V0-V31 */
#define FP_REGISTERS 32
#define CACHE_LINE_SIZE 64
#define CPU_CORES 8
/*
* vcpu_state_t - Holds the architectural state for an emulated vCPU.
* @r: General purpose registers R0-R30.
* @v: The 128-bit vector registers V0-V31.
* @r: General purpose registers R0-R31.
* @pc: Program Counter.
* @sp: Stack Pointer.
* @pstate: Process State Register (NZCV flags, EL, etc.).
*
* This structure is aligned to the L1 cache line size to prevent false
@ -27,9 +31,9 @@ namespace aarch64
*/
typedef struct alignas(CACHE_LINE_SIZE)
{
unsigned __int128 v[FP_REGISTERS];
uint64_t r[GP_REGISTERS];
uint64_t pc;
uint64_t sp;
uint32_t pstate;
} vcpu_state_t;
} // namespace aarch64