From e714dc47d0067a05acc699d1df7a615b61a15a13 Mon Sep 17 00:00:00 2001 From: Ronald Caesar Date: Fri, 5 Dec 2025 17:42:10 -0400 Subject: [PATCH 1/3] jit/decoder: rename decoder script Renames generate_decoder_tests.py to generate_jit_decoder_tests.py. Signed-off-by: Ronald Caesar --- CMakeLists.txt | 4 ++-- ...enerate_decoder_tests.py => generate_jit_decoder_tests.py} | 2 +- tests/jit/decoder/test_arm32_generated.cpp | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) rename scripts/{generate_decoder_tests.py => generate_jit_decoder_tests.py} (99%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 014d64b..f9e958a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -104,10 +104,10 @@ set(GEN_TEST_SRC ${CMAKE_CURRENT_SOURCE_DIR}/tests/jit/decoder/test_arm32_genera add_custom_command( OUTPUT ${GEN_TEST_SRC} - COMMAND Python3::Interpreter ${CMAKE_SOURCE_DIR}/scripts/generate_decoder_tests.py + COMMAND Python3::Interpreter ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_tests.py ${CMAKE_SOURCE_DIR}/src/jit/frontend/decoder/arm32.inc ${GEN_TEST_SRC} - DEPENDS ${CMAKE_SOURCE_DIR}/scripts/generate_decoder_tests.py + DEPENDS ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_tests.py ${CMAKE_SOURCE_DIR}/src/jit/frontend/decoder/arm32.inc COMMENT "Generating ARM32 Decoder Tests" ) diff --git a/scripts/generate_decoder_tests.py b/scripts/generate_jit_decoder_tests.py similarity index 99% rename from scripts/generate_decoder_tests.py rename to scripts/generate_jit_decoder_tests.py index 76ed9dc..e60a32f 100644 --- a/scripts/generate_decoder_tests.py +++ b/scripts/generate_jit_decoder_tests.py @@ -82,7 +82,7 @@ from typing import List, Dict, Optional, Tuple CPP_HEADER = """/* * GENERATED FILE - DO NOT EDIT * - * This file is generated by scripts/generate_decoder_tests.py + * This file is generated by scripts/generate_jit_decoder_tests.py * * PURPOSE: * Provides 100% requirements-based test coverage for the ARM32 Instruction Decoder. diff --git a/tests/jit/decoder/test_arm32_generated.cpp b/tests/jit/decoder/test_arm32_generated.cpp index eb64584..2cd8625 100644 --- a/tests/jit/decoder/test_arm32_generated.cpp +++ b/tests/jit/decoder/test_arm32_generated.cpp @@ -1,7 +1,7 @@ /* * GENERATED FILE - DO NOT EDIT * - * This file is generated by scripts/generate_decoder_tests.py + * This file is generated by scripts/generate_jit_decoder_tests.py * * PURPOSE: * Provides 100% requirements-based test coverage for the ARM32 Instruction Decoder. From b9b62574bfaeffff377e6768465144b4618f7872 Mon Sep 17 00:00:00 2001 From: Ronald Caesar Date: Sat, 6 Dec 2025 00:08:45 -0400 Subject: [PATCH 2/3] jit: Implement build-time generation of jit infrastructure generate_jit_assets.py expands the automatated code generation to include: - Opcode enumerations in arm32_opcodes.h. - Decoder lookup tables in arm32_table.c - Computed-goto jump tables foe the interpreter in handler_table.inc. Relocates arm32.inc to src/jit/common/a32_instructions.inc. Implements the primary execution loop in src/jit/interpreter/arm32/instruction.c. The code is messy and will be rewritten in the future. Signed-off-by: Ronald Caesar --- CMakeLists.txt | 4 +- scripts/generate_jit_assets.py | 242 ++++ scripts/generate_jit_decoder_a32_table.py | 147 -- src/jit/CMakeLists.txt | 36 +- .../arm32.inc => common/a32_instructions.inc} | 0 src/jit/frontend/decoder/arm32.c | 2 +- src/jit/frontend/decoder/arm32.h | 6 +- src/jit/frontend/decoder/arm32_opcodes.h | 260 ++++ ...{arm32_table_generated.c => arm32_table.c} | 523 ++++--- ...{arm32_table_generated.h => arm32_table.h} | 2 + src/jit/interpreter/a32/instruction.c | 3 - src/jit/interpreter/arm32/handler_table.inc | 252 ++++ src/jit/interpreter/arm32/handlers.inc | 1255 ++++++++++++++++ .../interpreter/arm32/handlers.inc.skeleton | 1261 +++++++++++++++++ src/jit/interpreter/arm32/instruction.c | 47 + .../interpreter/{a32 => arm32}/translator.c | 0 16 files changed, 3613 insertions(+), 427 deletions(-) create mode 100644 scripts/generate_jit_assets.py delete mode 100644 scripts/generate_jit_decoder_a32_table.py rename src/jit/{frontend/decoder/arm32.inc => common/a32_instructions.inc} (100%) create mode 100644 src/jit/frontend/decoder/arm32_opcodes.h rename src/jit/frontend/decoder/{arm32_table_generated.c => arm32_table.c} (92%) rename src/jit/frontend/decoder/{arm32_table_generated.h => arm32_table.h} (79%) delete mode 100644 src/jit/interpreter/a32/instruction.c create mode 100644 src/jit/interpreter/arm32/handler_table.inc create mode 100644 src/jit/interpreter/arm32/handlers.inc create mode 100644 src/jit/interpreter/arm32/handlers.inc.skeleton create mode 100644 src/jit/interpreter/arm32/instruction.c rename src/jit/interpreter/{a32 => arm32}/translator.c (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index f9e958a..797e6e3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -105,10 +105,10 @@ set(GEN_TEST_SRC ${CMAKE_CURRENT_SOURCE_DIR}/tests/jit/decoder/test_arm32_genera add_custom_command( OUTPUT ${GEN_TEST_SRC} COMMAND Python3::Interpreter ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_tests.py - ${CMAKE_SOURCE_DIR}/src/jit/frontend/decoder/arm32.inc + ${CMAKE_SOURCE_DIR}/src/jit/common/a32_instructions.inc ${GEN_TEST_SRC} DEPENDS ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_tests.py - ${CMAKE_SOURCE_DIR}/src/jit/frontend/decoder/arm32.inc + ${CMAKE_SOURCE_DIR}/src/jit/common/a32_instructions.inc COMMENT "Generating ARM32 Decoder Tests" ) diff --git a/scripts/generate_jit_assets.py b/scripts/generate_jit_assets.py new file mode 100644 index 0000000..a8b158b --- /dev/null +++ b/scripts/generate_jit_assets.py @@ -0,0 +1,242 @@ +#!/usr/bin/env python3 +import re +import sys +import argparse + +# Increased bucket size to handle overlapping wildcards +MAX_BUCKET_SIZE = 64 +TABLE_SIZE = 4096 + +# Bits [27:20] and [7:4] +HASH_BITS_MASK = 0x0FF000F0 + + +class Instruction: + def __init__(self, name, mnemonic, bitstring, array_index): + self.name = name + self.mnemonic = mnemonic + self.bitstring = bitstring + self.array_index = array_index + self.mask = 0 + self.expected = 0 + self.parse_bits() + + def parse_bits(self): + if len(self.bitstring) != 32: + print( + f"Error: Bitstring length {len(self.bitstring)} invalid for {self.name}" + ) + sys.exit(1) + + for i, char in enumerate(self.bitstring): + bit_pos = 31 - i + if char == "0": + self.mask |= 1 << bit_pos + elif char == "1": + self.mask |= 1 << bit_pos + self.expected |= 1 << bit_pos + # Variable bits (c, n, d, m, etc) leave mask as 0 + + +def parse_inc_file(input_path): + instructions = [] + regex = re.compile(r'INST\(\s*([A-Za-z0-9_]+),\s*"(.*?)",\s*"(.*?)"\s*\)') + + try: + with open(input_path, "r") as f: + lines = f.readlines() + except FileNotFoundError: + print(f"Error: Could not find input file: {input_path}") + sys.exit(1) + + index_counter = 0 + for line in lines: + line = line.strip() + if not line or line.startswith("//"): + continue + + match = regex.search(line) + if match: + inst = Instruction( + match.group(1), match.group(2), match.group(3), index_counter + ) + instructions.append(inst) + index_counter += 1 + return instructions + + +def generate_lookup_table(instructions): + buckets = {i: [] for i in range(TABLE_SIZE)} + + # Iterate over every possible hash index to determine which instructions belong in it + for i in range(TABLE_SIZE): + # Reconstruct the 32-bit value that would generate this hash index + # Hash algorithm: (Major << 4) | Minor + # Major is bits [27:20], Minor is bits [7:4] + + major_val = (i >> 4) & 0xFF + minor_val = i & 0x0F + + # Create a "Probe" value with the hash bits set + probe_val = (major_val << 20) | (minor_val << 4) + + for inst in instructions: + # Check if this instruction matches this hash index. + # An instruction matches if its FIXED bits (mask) match the Probe bits + # for the specific positions used by the hash. + + relevant_mask = inst.mask & HASH_BITS_MASK + relevant_expected = inst.expected & HASH_BITS_MASK + + if (probe_val & relevant_mask) == relevant_expected: + buckets[i].append(inst) + + if len(buckets[i]) > MAX_BUCKET_SIZE: + print( + f"FATAL ERROR: Bucket {i:#05x} overflowed! Size: {len(buckets[i])}" + ) + print( + "This means too many instructions map to the same hash index." + ) + sys.exit(1) + + return buckets + + +def write_decoder_table_h_file(path): + print(f"Generating decoder table header file: {path}") + with open(path, "w") as f: + f.write("/* GENERATED FILE - DO NOT EDIT */\n") + f.write("/* This file is generated by scripts/generate_jit_assets.py */\n") + f.write("#ifndef POUND_JIT_DECODER_ARM32_GENERATED_H\n") + f.write("#define POUND_JIT_DECODER_ARM32_GENERATED_H\n\n") + f.write('#include "arm32.h"\n') + f.write("#include \n\n") + f.write(f"#define LOOKUP_TABLE_MAX_BUCKET_SIZE {MAX_BUCKET_SIZE}U\n\n") + f.write("typedef struct {\n") + f.write( + " const pvm_jit_decoder_arm32_instruction_info_t *instructions[LOOKUP_TABLE_MAX_BUCKET_SIZE];\n" + ) + f.write(" size_t count;\n") + f.write("} decode_bucket_t;\n\n") + f.write( + f"extern const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}];\n\n" + ) + f.write("#endif\n") + + +def write_opcodes_header(path, instructions): + """Generates the arm32_opcodes.h file with a unique enum for each mnemonic.""" + print(f"Generating opcode header file: {path}") + seen = set() + with open(path, "w") as f: + f.write("/* GENERATED FILE - DO NOT EDIT */\n") + f.write("/* This file is generated by scripts/generate_jit_assets.py */\n") + f.write("#ifndef POUND_JIT_DECODER_ARM32_OPCODES_H\n") + f.write("#define POUND_JIT_DECODER_ARM32_OPCODES_H\n\n") + f.write("typedef enum {\n") + for inst in instructions: + enum_name = f" PVM_A32_OP_{inst.name.upper()},\n" + if enum_name not in seen: + f.write(enum_name) + seen.add(enum_name) + + f.write(" PVM_A32_OP_STOP,\n") + f.write("} pvm_jit_decoder_arm32_opcode_t;\n\n") + f.write("#endif // POUND_JIT_DECODER_ARM32_OPCODES_H\n") + + +def write_decoder_table_c_file(path, instructions, buckets): + """Writes the decoder C file, now including the opcode enum.""" + print(f"Generating decoder table source file: {path}") + with open(path, "w") as f: + f.write("/* GENERATED FILE - DO NOT EDIT */\n") + f.write("/* This file is generated by scripts/generate_jit_assets.py */\n") + f.write('#include "arm32.h"\n') + f.write('#include "arm32_table.h"\n\n') + f.write( + f"static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[{len(instructions)}] = {{\n" + ) + for inst in instructions: + f.write( + f' {{ "{inst.mnemonic}", "{inst.bitstring}", PVM_A32_OP_{inst.name.upper()}, {inst.mask:#010x}U, {inst.expected:#010x}U }},\n' + ) + f.write("};\n") + + f.write(f"const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}] = {{\n") + + for i in range(TABLE_SIZE): + if len(buckets[i]) > 0: + f.write(f" [{i:#05x}] = {{ .instructions = {{ ") + for inst in buckets[i]: + f.write(f"&g_instructions[{inst.array_index}], ") + f.write(f"}}, .count = {len(buckets[i])}U }},\n") + f.write("};\n") + + +def write_interpreter_handler_table(path, instructions): + """Generates the dispatch table.""" + print(f"Generating interpreter handler table: {path}") + seen = set() + with open(path, "w") as f: + f.write("/* GENERATED FILE - DO NOT EDIT */\n") + f.write("/* This file is generated by scripts/generate_jit_assets.py */\n") + for inst in instructions: + enum_name = f"PVM_A32_OP_{inst.name.upper()}" + if enum_name not in seen: + f.write(f" [{enum_name}] = &&HANDLER_{enum_name},\n") + seen.add(enum_name) + + +def write_interpreter_handler_skeletons(path, instructions): + """Generates a skeleton file for handlers.""" + + print(f"Generating new skeleton file: {path}") + seen = set() + with open(path, "w") as f: + f.write("/*\n") + f.write(" * GENERATED FILE - DO NOT EDIT\n") + f.write(" * This file is generated by scripts/generate_jit_assets.py \n") + f.write( + " * This file contains pre-generated, empty handler blocks for the every instruction.\n" + ) + f.write(" */\n\n") + for inst in instructions: + enum_name = f"HANDLER(PVM_A32_OP_{inst.name.upper()}): {{\n" + if enum_name not in seen: + f.write(enum_name) + seen.add(enum_name) + f.write(f" // TODO: Implement handler for {inst.mnemonic}\n") + f.write(" DISPATCH();\n") + f.write("}\n\n") + + f.write(f"HANDLER(PVM_A32_OP_STOP): {{\n") + f.write(f" // TODO: Implement handler for PVM_A32_OP_STOP\n") + f.write(" DISPATCH();\n") + f.write("}\n\n") + + +def main(): + parser = argparse.ArgumentParser(description="Generate ARM32 Decoder Tables") + parser.add_argument("input") + parser.add_argument("--out-opcodes-h") + parser.add_argument("--out-decoder-c") + parser.add_argument("--out-decoder-h") + parser.add_argument("--out-handler-table-inc") + parser.add_argument("--out-handler-skeletons-inc") + + args = parser.parse_args() + + instructions = parse_inc_file(args.input) + buckets = generate_lookup_table(instructions) + + # Generate all necessary files + write_opcodes_header(args.out_opcodes_h, instructions) + write_decoder_table_c_file(args.out_decoder_c, instructions, buckets) + write_decoder_table_h_file(args.out_decoder_h) + write_interpreter_handler_table(args.out_handler_table_inc, instructions) + write_interpreter_handler_skeletons(args.out_handler_skeletons_inc, instructions) + + +if __name__ == "__main__": + main() diff --git a/scripts/generate_jit_decoder_a32_table.py b/scripts/generate_jit_decoder_a32_table.py deleted file mode 100644 index b95cfa1..0000000 --- a/scripts/generate_jit_decoder_a32_table.py +++ /dev/null @@ -1,147 +0,0 @@ -#!/usr/bin/env python3 -import re -import sys -import argparse - -# Increased bucket size to handle overlapping wildcards -MAX_BUCKET_SIZE = 64 -TABLE_SIZE = 4096 - -# Bits [27:20] and [7:4] -HASH_BITS_MASK = 0x0FF000F0 - -class Instruction: - def __init__(self, name, mnemonic, bitstring, array_index): - self.name = name - self.mnemonic = mnemonic - self.bitstring = bitstring - self.array_index = array_index - self.mask = 0 - self.expected = 0 - self.parse_bits() - - def parse_bits(self): - if len(self.bitstring) != 32: - print(f"Error: Bitstring length {len(self.bitstring)} invalid for {self.name}") - sys.exit(1) - - for i, char in enumerate(self.bitstring): - bit_pos = 31 - i - if char == '0': - self.mask |= (1 << bit_pos) - elif char == '1': - self.mask |= (1 << bit_pos) - self.expected |= (1 << bit_pos) - # Variable bits (c, n, d, m, etc) leave mask as 0 - -def parse_inc_file(input_path): - instructions = [] - regex = re.compile(r'INST\(\s*([A-Za-z0-9_]+),\s*"(.*?)",\s*"(.*?)"\s*\)') - - try: - with open(input_path, 'r') as f: - lines = f.readlines() - except FileNotFoundError: - print(f"Error: Could not find input file: {input_path}") - sys.exit(1) - - index_counter = 0 - for line in lines: - line = line.strip() - if not line or line.startswith("//"): - continue - - match = regex.search(line) - if match: - inst = Instruction(match.group(1), match.group(2), match.group(3), index_counter) - instructions.append(inst) - index_counter += 1 - return instructions - -def generate_lookup_table(instructions): - buckets = {i: [] for i in range(TABLE_SIZE)} - - # Iterate over every possible hash index to determine which instructions belong in it - for i in range(TABLE_SIZE): - # Reconstruct the 32-bit value that would generate this hash index - # Hash algorithm: (Major << 4) | Minor - # Major is bits [27:20], Minor is bits [7:4] - - major_val = (i >> 4) & 0xFF - minor_val = i & 0x0F - - # Create a "Probe" value with the hash bits set - probe_val = (major_val << 20) | (minor_val << 4) - - for inst in instructions: - # Check if this instruction matches this hash index. - # An instruction matches if its FIXED bits (mask) match the Probe bits - # for the specific positions used by the hash. - - relevant_mask = inst.mask & HASH_BITS_MASK - relevant_expected = inst.expected & HASH_BITS_MASK - - if (probe_val & relevant_mask) == relevant_expected: - buckets[i].append(inst) - - if len(buckets[i]) > MAX_BUCKET_SIZE: - print(f"FATAL ERROR: Bucket {i:#05x} overflowed! Size: {len(buckets[i])}") - print("This means too many instructions map to the same hash index.") - sys.exit(1) - - return buckets - -def write_c_file(path, instructions, buckets): - with open(path, 'w') as f: - f.write("/* GENERATED FILE - DO NOT EDIT */\n") - f.write("/* This file is generated by scripts/generate_jit_decoder_a32_table.py */\n") - f.write('#include "arm32.h"\n') - f.write('#include "arm32_table_generated.h"\n\n') - - f.write(f"static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[{len(instructions)}] = {{\n") - for inst in instructions: - f.write(f' {{ "{inst.mnemonic}", "{inst.bitstring}", {inst.mask:#010x}U, {inst.expected:#010x}U }},\n') - f.write("};\n\n") - - f.write(f"const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}] = {{\n") - for i in range(TABLE_SIZE): - if len(buckets[i]) > 0: - f.write(f" [{i:#05x}] = {{ .instructions = {{ ") - for inst in buckets[i]: - f.write(f"&g_instructions[{inst.array_index}], ") - f.write(f"}}, .count = {len(buckets[i])}U }},\n") - f.write("};\n") - -def write_h_file(path): - with open(path, 'w') as f: - f.write("#ifndef POUND_JIT_DECODER_ARM32_GENERATED_H\n") - f.write("#define POUND_JIT_DECODER_ARM32_GENERATED_H\n\n") - f.write('#include "arm32.h"\n') - f.write('#include \n\n') - f.write(f"#define LOOKUP_TABLE_MAX_BUCKET_SIZE {MAX_BUCKET_SIZE}U\n\n") - f.write("typedef struct {\n") - f.write(" const pvm_jit_decoder_arm32_instruction_info_t *instructions[LOOKUP_TABLE_MAX_BUCKET_SIZE];\n") - f.write(" size_t count;\n") - f.write("} decode_bucket_t;\n\n") - f.write(f"extern const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}];\n\n") - f.write("#endif\n") - -# --------------------------------------------------------- -# Main Execution -# --------------------------------------------------------- - -def main(): - parser = argparse.ArgumentParser(description="Generate ARM32 Decoder Tables") - parser.add_argument("input", help="Path to arm32.inc") - parser.add_argument("out_c", help="Path to output .c file") - parser.add_argument("out_h", help="Path to output .h file") - args = parser.parse_args() - - print(f"{args.input} -> {args.out_c}") - instructions = parse_inc_file(args.input) - buckets = generate_lookup_table(instructions) - write_c_file(args.out_c, instructions, buckets) - write_h_file(args.out_h) - -if __name__ == "__main__": - main() diff --git a/src/jit/CMakeLists.txt b/src/jit/CMakeLists.txt index d06ae52..1298894 100644 --- a/src/jit/CMakeLists.txt +++ b/src/jit/CMakeLists.txt @@ -1,22 +1,30 @@ -# Define the generated files -set(GEN_SOURCE ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table_generated.c) -set(GEN_HEADER ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table_generated.h) -set(INC_FILE ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32.inc) -set(SCRIPT ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_a32_table.py) +# Define all the files that will be generated +set(GEN_OPCODES_H ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_opcodes.h) +set(GEN_DECODER_C ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table.c) +set(GEN_DECODER_H ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table.h) +set(GEN_HANDLER_TABLE ${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/handler_table.inc) +set(GEN_HANDLER_SKELETONS ${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/handlers.inc.skeleton) +set(INSTRUCTIONS ${CMAKE_CURRENT_SOURCE_DIR}/common/a32_instructions.inc) +set(SCRIPT ${CMAKE_SOURCE_DIR}/scripts/generate_jit_assets.py) add_custom_command( - OUTPUT ${GEN_SOURCE} ${GEN_HEADER} - COMMAND Python3::Interpreter ${SCRIPT} ${INC_FILE} ${GEN_SOURCE} ${GEN_HEADER} - DEPENDS ${SCRIPT} ${INC_FILE} - COMMENT "Generating ARM32 Decoder Tables" + OUTPUT ${GEN_OPCODES_H} ${GEN_DECODER_C} ${GEN_DECODER_H} ${GEN_HANDLER_TABLE} ${GEN_HANDLER_SKELETONS} + COMMAND Python3::Interpreter ${SCRIPT} ${INSTRUCTIONS} + --out-opcodes-h=${GEN_OPCODES_H} + --out-decoder-c=${GEN_DECODER_C} + --out-decoder-h=${GEN_DECODER_H} + --out-handler-table-inc=${GEN_HANDLER_TABLE} + --out-handler-skeletons-inc=${GEN_HANDLER_SKELETONS} + DEPENDS ${SCRIPT} ${INSTRUCTIONS} + COMMENT "Generating JIT assets" ) - add_library(jit STATIC) target_sources(jit PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32.c - ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table_generated.c + ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table.c + ${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/instruction.c ${CMAKE_CURRENT_SOURCE_DIR}/ir/type.c ${CMAKE_CURRENT_SOURCE_DIR}/ir/value.c ${CMAKE_CURRENT_SOURCE_DIR}/ir/opcode.c @@ -24,11 +32,17 @@ target_sources(jit PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ir/basic_block.c ) + set_source_files_properties( ${CMAKE_CURRENT_SOURCE_DIR}/ir/opcode.c PROPERTIES COMPILE_FLAGS "-Wno-c23-extensions -Wno-pedantic" ) +set_source_files_properties( + ${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/instruction.c + PROPERTIES COMPILE_FLAGS "-Wno-gnu-label-as-value -Wno-unused-label" +) + target_link_libraries(jit PRIVATE common host) target_include_directories(jit PUBLIC diff --git a/src/jit/frontend/decoder/arm32.inc b/src/jit/common/a32_instructions.inc similarity index 100% rename from src/jit/frontend/decoder/arm32.inc rename to src/jit/common/a32_instructions.inc diff --git a/src/jit/frontend/decoder/arm32.c b/src/jit/frontend/decoder/arm32.c index 20bf83f..f05b4c9 100644 --- a/src/jit/frontend/decoder/arm32.c +++ b/src/jit/frontend/decoder/arm32.c @@ -1,5 +1,5 @@ #include "arm32.h" -#include "arm32_table_generated.h" +#include "arm32_table.h" #include "common/passert.h" #include #include diff --git a/src/jit/frontend/decoder/arm32.h b/src/jit/frontend/decoder/arm32.h index 239cd3d..8ddc3e3 100644 --- a/src/jit/frontend/decoder/arm32.h +++ b/src/jit/frontend/decoder/arm32.h @@ -11,6 +11,7 @@ #ifndef POUND_JIT_DECODER_ARM32_H #define POUND_JIT_DECODER_ARM32_H +#include "arm32_opcodes.h" #include /* Extern C for unit tests. */ @@ -22,9 +23,9 @@ extern "C" { * instruction. */ typedef struct { + /*! @brief The instruction mnemonic (e.g., "ADD", "LDR"). */ const char *name; - /*! * @brief The raw bitstring representation. * @details Used during initialization to calculate mask and expected @@ -32,6 +33,9 @@ typedef struct */ const char *bitstring; + /*! @brief The instruction's unique enum identifier. */ + pvm_jit_decoder_arm32_opcode_t opcode; + /*! * @brief The bitmask indicating which bits in the instruction word are * significant. diff --git a/src/jit/frontend/decoder/arm32_opcodes.h b/src/jit/frontend/decoder/arm32_opcodes.h new file mode 100644 index 0000000..660d3e2 --- /dev/null +++ b/src/jit/frontend/decoder/arm32_opcodes.h @@ -0,0 +1,260 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* This file is generated by scripts/generate_jit_assets.py */ +#ifndef POUND_JIT_DECODER_ARM32_OPCODES_H +#define POUND_JIT_DECODER_ARM32_OPCODES_H + +typedef enum { + PVM_A32_OP_DMB, + PVM_A32_OP_DSB, + PVM_A32_OP_ISB, + PVM_A32_OP_BLX_IMM, + PVM_A32_OP_BLX_REG, + PVM_A32_OP_B, + PVM_A32_OP_BL, + PVM_A32_OP_BX, + PVM_A32_OP_BXJ, + PVM_A32_OP_RFE, + PVM_A32_OP_SRS, + PVM_A32_OP_CPS, + PVM_A32_OP_SETEND, + PVM_A32_OP_CRC32, + PVM_A32_OP_CRC32C, + PVM_A32_OP_CDP, + PVM_A32_OP_MCR, + PVM_A32_OP_MCRR, + PVM_A32_OP_MRC, + PVM_A32_OP_MRRC, + PVM_A32_OP_LDC, + PVM_A32_OP_STC, + PVM_A32_OP_ADC_IMM, + PVM_A32_OP_ADC_REG, + PVM_A32_OP_ADC_RSR, + PVM_A32_OP_ADD_IMM, + PVM_A32_OP_ADD_REG, + PVM_A32_OP_ADD_RSR, + PVM_A32_OP_AND_IMM, + PVM_A32_OP_AND_REG, + PVM_A32_OP_AND_RSR, + PVM_A32_OP_BIC_IMM, + PVM_A32_OP_BIC_REG, + PVM_A32_OP_BIC_RSR, + PVM_A32_OP_CMN_IMM, + PVM_A32_OP_CMN_REG, + PVM_A32_OP_CMN_RSR, + PVM_A32_OP_CMP_IMM, + PVM_A32_OP_CMP_REG, + PVM_A32_OP_CMP_RSR, + PVM_A32_OP_EOR_IMM, + PVM_A32_OP_EOR_REG, + PVM_A32_OP_EOR_RSR, + PVM_A32_OP_MOV_IMM, + PVM_A32_OP_MOV_REG, + PVM_A32_OP_MOV_RSR, + PVM_A32_OP_MVN_IMM, + PVM_A32_OP_MVN_REG, + PVM_A32_OP_MVN_RSR, + PVM_A32_OP_ORR_IMM, + PVM_A32_OP_ORR_REG, + PVM_A32_OP_ORR_RSR, + PVM_A32_OP_RSB_IMM, + PVM_A32_OP_RSB_REG, + PVM_A32_OP_RSB_RSR, + PVM_A32_OP_RSC_IMM, + PVM_A32_OP_RSC_REG, + PVM_A32_OP_RSC_RSR, + PVM_A32_OP_SBC_IMM, + PVM_A32_OP_SBC_REG, + PVM_A32_OP_SBC_RSR, + PVM_A32_OP_SUB_IMM, + PVM_A32_OP_SUB_REG, + PVM_A32_OP_SUB_RSR, + PVM_A32_OP_TEQ_IMM, + PVM_A32_OP_TEQ_REG, + PVM_A32_OP_TEQ_RSR, + PVM_A32_OP_TST_IMM, + PVM_A32_OP_TST_REG, + PVM_A32_OP_TST_RSR, + PVM_A32_OP_BKPT, + PVM_A32_OP_SVC, + PVM_A32_OP_UDF, + PVM_A32_OP_SXTB, + PVM_A32_OP_SXTB16, + PVM_A32_OP_SXTH, + PVM_A32_OP_SXTAB, + PVM_A32_OP_SXTAB16, + PVM_A32_OP_SXTAH, + PVM_A32_OP_UXTB, + PVM_A32_OP_UXTB16, + PVM_A32_OP_UXTH, + PVM_A32_OP_UXTAB, + PVM_A32_OP_UXTAB16, + PVM_A32_OP_UXTAH, + PVM_A32_OP_PLD_IMM, + PVM_A32_OP_PLD_REG, + PVM_A32_OP_SEV, + PVM_A32_OP_SEVL, + PVM_A32_OP_WFE, + PVM_A32_OP_WFI, + PVM_A32_OP_YIELD, + PVM_A32_OP_NOP, + PVM_A32_OP_CLREX, + PVM_A32_OP_SWP, + PVM_A32_OP_SWPB, + PVM_A32_OP_STL, + PVM_A32_OP_STLEX, + PVM_A32_OP_STREX, + PVM_A32_OP_LDA, + PVM_A32_OP_LDAEX, + PVM_A32_OP_LDREX, + PVM_A32_OP_STLEXD, + PVM_A32_OP_STREXD, + PVM_A32_OP_LDAEXD, + PVM_A32_OP_LDREXD, + PVM_A32_OP_STLB, + PVM_A32_OP_STLEXB, + PVM_A32_OP_STREXB, + PVM_A32_OP_LDAB, + PVM_A32_OP_LDAEXB, + PVM_A32_OP_LDREXB, + PVM_A32_OP_STLH, + PVM_A32_OP_STLEXH, + PVM_A32_OP_STREXH, + PVM_A32_OP_LDAH, + PVM_A32_OP_LDAEXH, + PVM_A32_OP_LDREXH, + PVM_A32_OP_LDRBT, + PVM_A32_OP_LDRHT, + PVM_A32_OP_LDRSBT, + PVM_A32_OP_LDRSHT, + PVM_A32_OP_LDRT, + PVM_A32_OP_STRBT, + PVM_A32_OP_STRHT, + PVM_A32_OP_STRT, + PVM_A32_OP_LDR_LIT, + PVM_A32_OP_LDR_IMM, + PVM_A32_OP_LDR_REG, + PVM_A32_OP_LDRB_LIT, + PVM_A32_OP_LDRB_IMM, + PVM_A32_OP_LDRB_REG, + PVM_A32_OP_LDRD_LIT, + PVM_A32_OP_LDRD_IMM, + PVM_A32_OP_LDRD_REG, + PVM_A32_OP_LDRH_LIT, + PVM_A32_OP_LDRH_IMM, + PVM_A32_OP_LDRH_REG, + PVM_A32_OP_LDRSB_LIT, + PVM_A32_OP_LDRSB_IMM, + PVM_A32_OP_LDRSB_REG, + PVM_A32_OP_LDRSH_LIT, + PVM_A32_OP_LDRSH_IMM, + PVM_A32_OP_LDRSH_REG, + PVM_A32_OP_STR_IMM, + PVM_A32_OP_STR_REG, + PVM_A32_OP_STRB_IMM, + PVM_A32_OP_STRB_REG, + PVM_A32_OP_STRD_IMM, + PVM_A32_OP_STRD_REG, + PVM_A32_OP_STRH_IMM, + PVM_A32_OP_STRH_REG, + PVM_A32_OP_LDM, + PVM_A32_OP_LDMDA, + PVM_A32_OP_LDMDB, + PVM_A32_OP_LDMIB, + PVM_A32_OP_LDM_USR, + PVM_A32_OP_LDM_ERET, + PVM_A32_OP_STM, + PVM_A32_OP_STMDA, + PVM_A32_OP_STMDB, + PVM_A32_OP_STMIB, + PVM_A32_OP_STM_USR, + PVM_A32_OP_BFC, + PVM_A32_OP_BFI, + PVM_A32_OP_CLZ, + PVM_A32_OP_MOVT, + PVM_A32_OP_MOVW, + PVM_A32_OP_SBFX, + PVM_A32_OP_SEL, + PVM_A32_OP_UBFX, + PVM_A32_OP_USAD8, + PVM_A32_OP_USADA8, + PVM_A32_OP_PKHBT, + PVM_A32_OP_PKHTB, + PVM_A32_OP_RBIT, + PVM_A32_OP_REV, + PVM_A32_OP_REV16, + PVM_A32_OP_REVSH, + PVM_A32_OP_SSAT, + PVM_A32_OP_SSAT16, + PVM_A32_OP_USAT, + PVM_A32_OP_USAT16, + PVM_A32_OP_SDIV, + PVM_A32_OP_UDIV, + PVM_A32_OP_MLA, + PVM_A32_OP_MLS, + PVM_A32_OP_MUL, + PVM_A32_OP_SMLAL, + PVM_A32_OP_SMULL, + PVM_A32_OP_UMAAL, + PVM_A32_OP_UMLAL, + PVM_A32_OP_UMULL, + PVM_A32_OP_SMLALXY, + PVM_A32_OP_SMLAXY, + PVM_A32_OP_SMULXY, + PVM_A32_OP_SMLAWY, + PVM_A32_OP_SMULWY, + PVM_A32_OP_SMMUL, + PVM_A32_OP_SMMLA, + PVM_A32_OP_SMMLS, + PVM_A32_OP_SMUAD, + PVM_A32_OP_SMLAD, + PVM_A32_OP_SMLALD, + PVM_A32_OP_SMUSD, + PVM_A32_OP_SMLSD, + PVM_A32_OP_SMLSLD, + PVM_A32_OP_SADD8, + PVM_A32_OP_SADD16, + PVM_A32_OP_SASX, + PVM_A32_OP_SSAX, + PVM_A32_OP_SSUB8, + PVM_A32_OP_SSUB16, + PVM_A32_OP_UADD8, + PVM_A32_OP_UADD16, + PVM_A32_OP_UASX, + PVM_A32_OP_USAX, + PVM_A32_OP_USUB8, + PVM_A32_OP_USUB16, + PVM_A32_OP_QADD8, + PVM_A32_OP_QADD16, + PVM_A32_OP_QASX, + PVM_A32_OP_QSAX, + PVM_A32_OP_QSUB8, + PVM_A32_OP_QSUB16, + PVM_A32_OP_UQADD8, + PVM_A32_OP_UQADD16, + PVM_A32_OP_UQASX, + PVM_A32_OP_UQSAX, + PVM_A32_OP_UQSUB8, + PVM_A32_OP_UQSUB16, + PVM_A32_OP_SHADD8, + PVM_A32_OP_SHADD16, + PVM_A32_OP_SHASX, + PVM_A32_OP_SHSAX, + PVM_A32_OP_SHSUB8, + PVM_A32_OP_SHSUB16, + PVM_A32_OP_UHADD8, + PVM_A32_OP_UHADD16, + PVM_A32_OP_UHASX, + PVM_A32_OP_UHSAX, + PVM_A32_OP_UHSUB8, + PVM_A32_OP_UHSUB16, + PVM_A32_OP_QADD, + PVM_A32_OP_QSUB, + PVM_A32_OP_QDADD, + PVM_A32_OP_QDSUB, + PVM_A32_OP_MRS, + PVM_A32_OP_MSR_IMM, + PVM_A32_OP_MSR_REG, + PVM_A32_OP_STOP, +} pvm_jit_decoder_arm32_opcode_t; + +#endif // POUND_JIT_DECODER_ARM32_OPCODES_H diff --git a/src/jit/frontend/decoder/arm32_table_generated.c b/src/jit/frontend/decoder/arm32_table.c similarity index 92% rename from src/jit/frontend/decoder/arm32_table_generated.c rename to src/jit/frontend/decoder/arm32_table.c index 61bdd63..2d28f57 100644 --- a/src/jit/frontend/decoder/arm32_table_generated.c +++ b/src/jit/frontend/decoder/arm32_table.c @@ -1,270 +1,269 @@ /* GENERATED FILE - DO NOT EDIT */ -/* This file is generated by scripts/generate_jit_decoder_a32_table.py */ +/* This file is generated by scripts/generate_jit_assets.py */ #include "arm32.h" -#include "arm32_table_generated.h" +#include "arm32_table.h" static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[259] = { - { "DMB", "1111010101111111111100000101oooo", 0xfffffff0U, 0xf57ff050U }, - { "DSB", "1111010101111111111100000100oooo", 0xfffffff0U, 0xf57ff040U }, - { "ISB", "1111010101111111111100000110oooo", 0xfffffff0U, 0xf57ff060U }, - { "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv", 0xfe000000U, 0xfa000000U }, - { "BLX (reg)", "cccc000100101111111111110011mmmm", 0x0ffffff0U, 0x012fff30U }, - { "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0a000000U }, - { "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0b000000U }, - { "BX", "cccc000100101111111111110001mmmm", 0x0ffffff0U, 0x012fff10U }, - { "BXJ", "cccc000100101111111111110010mmmm", 0x0ffffff0U, 0x012fff20U }, - { "RFE", "1111100--0-1----0000101000000000", 0xfe50ffffU, 0xf8100a00U }, - { "SRS", "1111100--1-0110100000101000-----", 0xfe5fffe0U, 0xf84d0500U }, - { "CPS", "111100010000---00000000---0-----", 0xfff1fe20U, 0xf1000000U }, - { "SETEND", "1111000100000001000000e000000000", 0xfffffdffU, 0xf1010000U }, - { "CRC32", "cccc00010zz0nnnndddd00000100mmmm", 0x0f900ff0U, 0x01000040U }, - { "CRC32C", "cccc00010zz0nnnndddd00100100mmmm", 0x0f900ff0U, 0x01000240U }, - { "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM", 0x0f000010U, 0x0e000000U }, - { "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM", 0x0f100010U, 0x0e000010U }, - { "MCRR", "cccc11000100uuuuttttppppooooMMMM", 0x0ff00000U, 0x0c400000U }, - { "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM", 0x0f100010U, 0x0e100010U }, - { "MRRC", "cccc11000101uuuuttttppppooooMMMM", 0x0ff00000U, 0x0c500000U }, - { "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv", 0x0e100000U, 0x0c100000U }, - { "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv", 0x0e100000U, 0x0c000000U }, - { "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02a00000U }, - { "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00a00000U }, - { "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00a00010U }, - { "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02800000U }, - { "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00800000U }, - { "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00800010U }, - { "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02000000U }, - { "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00000000U }, - { "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00000010U }, - { "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x03c00000U }, - { "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x01c00000U }, - { "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x01c00010U }, - { "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03700000U }, - { "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01700000U }, - { "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01700010U }, - { "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03500000U }, - { "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01500000U }, - { "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01500010U }, - { "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02200000U }, - { "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00200000U }, - { "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00200010U }, - { "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv", 0x0fef0000U, 0x03a00000U }, - { "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm", 0x0fef0010U, 0x01a00000U }, - { "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm", 0x0fef0090U, 0x01a00010U }, - { "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv", 0x0fef0000U, 0x03e00000U }, - { "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm", 0x0fef0010U, 0x01e00000U }, - { "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm", 0x0fef0090U, 0x01e00010U }, - { "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x03800000U }, - { "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x01800000U }, - { "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x01800010U }, - { "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02600000U }, - { "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00600000U }, - { "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00600010U }, - { "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02e00000U }, - { "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00e00000U }, - { "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00e00010U }, - { "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02c00000U }, - { "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00c00000U }, - { "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00c00010U }, - { "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02400000U }, - { "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00400000U }, - { "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00400010U }, - { "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03300000U }, - { "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01300000U }, - { "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01300010U }, - { "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03100000U }, - { "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01100000U }, - { "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01100010U }, - { "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv", 0x0ff000f0U, 0x01200070U }, - { "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0f000000U }, - { "UDF", "111001111111------------1111----", 0xfff000f0U, 0xe7f000f0U }, - { "SXTB", "cccc011010101111ddddrr000111mmmm", 0x0fff03f0U, 0x06af0070U }, - { "SXTB16", "cccc011010001111ddddrr000111mmmm", 0x0fff03f0U, 0x068f0070U }, - { "SXTH", "cccc011010111111ddddrr000111mmmm", 0x0fff03f0U, 0x06bf0070U }, - { "SXTAB", "cccc01101010nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06a00070U }, - { "SXTAB16", "cccc01101000nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06800070U }, - { "SXTAH", "cccc01101011nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06b00070U }, - { "UXTB", "cccc011011101111ddddrr000111mmmm", 0x0fff03f0U, 0x06ef0070U }, - { "UXTB16", "cccc011011001111ddddrr000111mmmm", 0x0fff03f0U, 0x06cf0070U }, - { "UXTH", "cccc011011111111ddddrr000111mmmm", 0x0fff03f0U, 0x06ff0070U }, - { "UXTAB", "cccc01101110nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06e00070U }, - { "UXTAB16", "cccc01101100nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06c00070U }, - { "UXTAH", "cccc01101111nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06f00070U }, - { "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii", 0xff30f000U, 0xf510f000U }, - { "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm", 0xff30f010U, 0xf710f000U }, - { "SEV", "----0011001000001111000000000100", 0x0fffffffU, 0x0320f004U }, - { "SEVL", "----0011001000001111000000000101", 0x0fffffffU, 0x0320f005U }, - { "WFE", "----0011001000001111000000000010", 0x0fffffffU, 0x0320f002U }, - { "WFI", "----0011001000001111000000000011", 0x0fffffffU, 0x0320f003U }, - { "YIELD", "----0011001000001111000000000001", 0x0fffffffU, 0x0320f001U }, - { "NOP", "----0011001000001111000000000000", 0x0fffffffU, 0x0320f000U }, - { "CLREX", "11110101011111111111000000011111", 0xffffffffU, 0xf57ff01fU }, - { "SWP", "cccc00010000nnnntttt00001001uuuu", 0x0ff00ff0U, 0x01000090U }, - { "SWPB", "cccc00010100nnnntttt00001001uuuu", 0x0ff00ff0U, 0x01400090U }, - { "STL", "cccc00011000nnnn111111001001tttt", 0x0ff0fff0U, 0x0180fc90U }, - { "STLEX", "cccc00011000nnnndddd11101001tttt", 0x0ff00ff0U, 0x01800e90U }, - { "STREX", "cccc00011000nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01800f90U }, - { "LDA", "cccc00011001nnnndddd110010011111", 0x0ff00fffU, 0x01900c9fU }, - { "LDAEX", "cccc00011001nnnndddd111010011111", 0x0ff00fffU, 0x01900e9fU }, - { "LDREX", "cccc00011001nnnndddd111110011111", 0x0ff00fffU, 0x01900f9fU }, - { "STLEXD", "cccc00011010nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01a00e90U }, - { "STREXD", "cccc00011010nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01a00f90U }, - { "LDAEXD", "cccc00011011nnnndddd111010011111", 0x0ff00fffU, 0x01b00e9fU }, - { "LDREXD", "cccc00011011nnnndddd111110011111", 0x0ff00fffU, 0x01b00f9fU }, - { "STLB", "cccc00011100nnnn111111001001tttt", 0x0ff0fff0U, 0x01c0fc90U }, - { "STLEXB", "cccc00011100nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01c00e90U }, - { "STREXB", "cccc00011100nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01c00f90U }, - { "LDAB", "cccc00011101nnnndddd110010011111", 0x0ff00fffU, 0x01d00c9fU }, - { "LDAEXB", "cccc00011101nnnndddd111010011111", 0x0ff00fffU, 0x01d00e9fU }, - { "LDREXB", "cccc00011101nnnndddd111110011111", 0x0ff00fffU, 0x01d00f9fU }, - { "STLH", "cccc00011110nnnn111111001001mmmm", 0x0ff0fff0U, 0x01e0fc90U }, - { "STLEXH", "cccc00011110nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01e00e90U }, - { "STREXH", "cccc00011110nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01e00f90U }, - { "LDAH", "cccc00011111nnnndddd110010011111", 0x0ff00fffU, 0x01f00c9fU }, - { "LDAEXH", "cccc00011111nnnndddd111010011111", 0x0ff00fffU, 0x01f00e9fU }, - { "LDREXH", "cccc00011111nnnndddd111110011111", 0x0ff00fffU, 0x01f00f9fU }, - { "LDRBT (A1)", "----0100-111--------------------", 0x0f700000U, 0x04700000U }, - { "LDRBT (A2)", "----0110-111---------------0----", 0x0f700010U, 0x06700000U }, - { "LDRHT (A1)", "----0000-111------------1011----", 0x0f7000f0U, 0x007000b0U }, - { "LDRHT (A1)", "----0000-1111111--------1011----", 0x0f7f00f0U, 0x007f00b0U }, - { "LDRHT (A2)", "----0000-011--------00001011----", 0x0f700ff0U, 0x003000b0U }, - { "LDRSBT (A1)", "----0000-111------------1101----", 0x0f7000f0U, 0x007000d0U }, - { "LDRSBT (A2)", "----0000-011--------00001101----", 0x0f700ff0U, 0x003000d0U }, - { "LDRSHT (A1)", "----0000-111------------1111----", 0x0f7000f0U, 0x007000f0U }, - { "LDRSHT (A2)", "----0000-011--------00001111----", 0x0f700ff0U, 0x003000f0U }, - { "LDRT (A1)", "----0100-011--------------------", 0x0f700000U, 0x04300000U }, - { "LDRT (A2)", "----0110-011---------------0----", 0x0f700010U, 0x06300000U }, - { "STRBT (A1)", "----0100-110--------------------", 0x0f700000U, 0x04600000U }, - { "STRBT (A2)", "----0110-110---------------0----", 0x0f700010U, 0x06600000U }, - { "STRHT (A1)", "----0000-110------------1011----", 0x0f7000f0U, 0x006000b0U }, - { "STRHT (A2)", "----0000-010--------00001011----", 0x0f700ff0U, 0x002000b0U }, - { "STRT (A1)", "----0100-010--------------------", 0x0f700000U, 0x04200000U }, - { "STRT (A2)", "----0110-010---------------0----", 0x0f700010U, 0x06200000U }, - { "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv", 0x0f7f0000U, 0x051f0000U }, - { "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04100000U }, - { "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06100000U }, - { "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv", 0x0f7f0000U, 0x055f0000U }, - { "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04500000U }, - { "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06500000U }, - { "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv", 0x0f7f00f0U, 0x014f00d0U }, - { "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv", 0x0e5000f0U, 0x004000d0U }, - { "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm", 0x0e500ff0U, 0x000000d0U }, - { "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv", 0x0e5f00f0U, 0x005f00b0U }, - { "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv", 0x0e5000f0U, 0x005000b0U }, - { "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm", 0x0e500ff0U, 0x001000b0U }, - { "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv", 0x0f7f00f0U, 0x015f00d0U }, - { "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv", 0x0e5000f0U, 0x005000d0U }, - { "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm", 0x0e500ff0U, 0x001000d0U }, - { "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv", 0x0f7f00f0U, 0x015f00f0U }, - { "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv", 0x0e5000f0U, 0x005000f0U }, - { "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm", 0x0e500ff0U, 0x001000f0U }, - { "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04000000U }, - { "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06000000U }, - { "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04400000U }, - { "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06400000U }, - { "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv", 0x0e5000f0U, 0x004000f0U }, - { "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm", 0x0e500ff0U, 0x000000f0U }, - { "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv", 0x0e5000f0U, 0x004000b0U }, - { "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm", 0x0e500ff0U, 0x000000b0U }, - { "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08900000U }, - { "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08100000U }, - { "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09100000U }, - { "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09900000U }, - { "LDM (usr reg)", "----100--101----0---------------", 0x0e708000U, 0x08500000U }, - { "LDM (exce ret)", "----100--1-1----1---------------", 0x0e508000U, 0x08508000U }, - { "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08800000U }, - { "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08000000U }, - { "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09000000U }, - { "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09800000U }, - { "STM (usr reg)", "----100--100--------------------", 0x0e700000U, 0x08400000U }, - { "BFC", "cccc0111110vvvvvddddvvvvv0011111", 0x0fe0007fU, 0x07c0001fU }, - { "BFI", "cccc0111110vvvvvddddvvvvv001nnnn", 0x0fe00070U, 0x07c00010U }, - { "CLZ", "cccc000101101111dddd11110001mmmm", 0x0fff0ff0U, 0x016f0f10U }, - { "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv", 0x0ff00000U, 0x03400000U }, - { "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv", 0x0ff00000U, 0x03000000U }, - { "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn", 0x0fe00070U, 0x07a00050U }, - { "SEL", "cccc01101000nnnndddd11111011mmmm", 0x0ff00ff0U, 0x06800fb0U }, - { "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn", 0x0fe00070U, 0x07e00050U }, - { "USAD8", "cccc01111000dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0780f010U }, - { "USADA8", "cccc01111000ddddaaaammmm0001nnnn", 0x0ff000f0U, 0x07800010U }, - { "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm", 0x0ff00070U, 0x06800010U }, - { "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm", 0x0ff00070U, 0x06800050U }, - { "RBIT", "cccc011011111111dddd11110011mmmm", 0x0fff0ff0U, 0x06ff0f30U }, - { "REV", "cccc011010111111dddd11110011mmmm", 0x0fff0ff0U, 0x06bf0f30U }, - { "REV16", "cccc011010111111dddd11111011mmmm", 0x0fff0ff0U, 0x06bf0fb0U }, - { "REVSH", "cccc011011111111dddd11111011mmmm", 0x0fff0ff0U, 0x06ff0fb0U }, - { "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn", 0x0fe00030U, 0x06a00010U }, - { "SSAT16", "cccc01101010vvvvdddd11110011nnnn", 0x0ff00ff0U, 0x06a00f30U }, - { "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn", 0x0fe00030U, 0x06e00010U }, - { "USAT16", "cccc01101110vvvvdddd11110011nnnn", 0x0ff00ff0U, 0x06e00f30U }, - { "SDIV", "cccc01110001dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0710f010U }, - { "UDIV", "cccc01110011dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0730f010U }, - { "MLA", "cccc0000001Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00200090U }, - { "MLS", "cccc00000110ddddaaaammmm1001nnnn", 0x0ff000f0U, 0x00600090U }, - { "MUL", "cccc0000000Sdddd0000mmmm1001nnnn", 0x0fe0f0f0U, 0x00000090U }, - { "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00e00090U }, - { "SMULL", "cccc0000110Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00c00090U }, - { "UMAAL", "cccc00000100ddddaaaammmm1001nnnn", 0x0ff000f0U, 0x00400090U }, - { "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00a00090U }, - { "UMULL", "cccc0000100Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00800090U }, - { "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn", 0x0ff00090U, 0x01400080U }, - { "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn", 0x0ff00090U, 0x01000080U }, - { "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn", 0x0ff0f090U, 0x01600080U }, - { "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn", 0x0ff000b0U, 0x01200080U }, - { "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn", 0x0ff0f0b0U, 0x012000a0U }, - { "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn", 0x0ff0f0d0U, 0x0750f010U }, - { "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn", 0x0ff000d0U, 0x07500010U }, - { "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn", 0x0ff000d0U, 0x075000d0U }, - { "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn", 0x0ff0f0d0U, 0x0700f010U }, - { "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn", 0x0ff000d0U, 0x07000010U }, - { "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn", 0x0ff000d0U, 0x07400010U }, - { "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn", 0x0ff0f0d0U, 0x0700f050U }, - { "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn", 0x0ff000d0U, 0x07000050U }, - { "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn", 0x0ff000d0U, 0x07400050U }, - { "SADD8", "cccc01100001nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06100f90U }, - { "SADD16", "cccc01100001nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06100f10U }, - { "SASX", "cccc01100001nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06100f30U }, - { "SSAX", "cccc01100001nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06100f50U }, - { "SSUB8", "cccc01100001nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06100ff0U }, - { "SSUB16", "cccc01100001nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06100f70U }, - { "UADD8", "cccc01100101nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06500f90U }, - { "UADD16", "cccc01100101nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06500f10U }, - { "UASX", "cccc01100101nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06500f30U }, - { "USAX", "cccc01100101nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06500f50U }, - { "USUB8", "cccc01100101nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06500ff0U }, - { "USUB16", "cccc01100101nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06500f70U }, - { "QADD8", "cccc01100010nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06200f90U }, - { "QADD16", "cccc01100010nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06200f10U }, - { "QASX", "cccc01100010nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06200f30U }, - { "QSAX", "cccc01100010nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06200f50U }, - { "QSUB8", "cccc01100010nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06200ff0U }, - { "QSUB16", "cccc01100010nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06200f70U }, - { "UQADD8", "cccc01100110nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06600f90U }, - { "UQADD16", "cccc01100110nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06600f10U }, - { "UQASX", "cccc01100110nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06600f30U }, - { "UQSAX", "cccc01100110nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06600f50U }, - { "UQSUB8", "cccc01100110nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06600ff0U }, - { "UQSUB16", "cccc01100110nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06600f70U }, - { "SHADD8", "cccc01100011nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06300f90U }, - { "SHADD16", "cccc01100011nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06300f10U }, - { "SHASX", "cccc01100011nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06300f30U }, - { "SHSAX", "cccc01100011nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06300f50U }, - { "SHSUB8", "cccc01100011nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06300ff0U }, - { "SHSUB16", "cccc01100011nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06300f70U }, - { "UHADD8", "cccc01100111nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06700f90U }, - { "UHADD16", "cccc01100111nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06700f10U }, - { "UHASX", "cccc01100111nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06700f30U }, - { "UHSAX", "cccc01100111nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06700f50U }, - { "UHSUB8", "cccc01100111nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06700ff0U }, - { "UHSUB16", "cccc01100111nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06700f70U }, - { "QADD", "cccc00010000nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01000050U }, - { "QSUB", "cccc00010010nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01200050U }, - { "QDADD", "cccc00010100nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01400050U }, - { "QDSUB", "cccc00010110nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01600050U }, - { "MRS", "cccc000100001111dddd000000000000", 0x0fff0fffU, 0x010f0000U }, - { "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv", 0x0ff0f000U, 0x0320f000U }, - { "MSR (reg)", "cccc00010010mmmm111100000000nnnn", 0x0ff0fff0U, 0x0120f000U }, + { "DMB", "1111010101111111111100000101oooo", PVM_A32_OP_DMB, 0xfffffff0U, 0xf57ff050U }, + { "DSB", "1111010101111111111100000100oooo", PVM_A32_OP_DSB, 0xfffffff0U, 0xf57ff040U }, + { "ISB", "1111010101111111111100000110oooo", PVM_A32_OP_ISB, 0xfffffff0U, 0xf57ff060U }, + { "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_BLX_IMM, 0xfe000000U, 0xfa000000U }, + { "BLX (reg)", "cccc000100101111111111110011mmmm", PVM_A32_OP_BLX_REG, 0x0ffffff0U, 0x012fff30U }, + { "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_B, 0x0f000000U, 0x0a000000U }, + { "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_BL, 0x0f000000U, 0x0b000000U }, + { "BX", "cccc000100101111111111110001mmmm", PVM_A32_OP_BX, 0x0ffffff0U, 0x012fff10U }, + { "BXJ", "cccc000100101111111111110010mmmm", PVM_A32_OP_BXJ, 0x0ffffff0U, 0x012fff20U }, + { "RFE", "1111100--0-1----0000101000000000", PVM_A32_OP_RFE, 0xfe50ffffU, 0xf8100a00U }, + { "SRS", "1111100--1-0110100000101000-----", PVM_A32_OP_SRS, 0xfe5fffe0U, 0xf84d0500U }, + { "CPS", "111100010000---00000000---0-----", PVM_A32_OP_CPS, 0xfff1fe20U, 0xf1000000U }, + { "SETEND", "1111000100000001000000e000000000", PVM_A32_OP_SETEND, 0xfffffdffU, 0xf1010000U }, + { "CRC32", "cccc00010zz0nnnndddd00000100mmmm", PVM_A32_OP_CRC32, 0x0f900ff0U, 0x01000040U }, + { "CRC32C", "cccc00010zz0nnnndddd00100100mmmm", PVM_A32_OP_CRC32C, 0x0f900ff0U, 0x01000240U }, + { "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM", PVM_A32_OP_CDP, 0x0f000010U, 0x0e000000U }, + { "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM", PVM_A32_OP_MCR, 0x0f100010U, 0x0e000010U }, + { "MCRR", "cccc11000100uuuuttttppppooooMMMM", PVM_A32_OP_MCRR, 0x0ff00000U, 0x0c400000U }, + { "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM", PVM_A32_OP_MRC, 0x0f100010U, 0x0e100010U }, + { "MRRC", "cccc11000101uuuuttttppppooooMMMM", PVM_A32_OP_MRRC, 0x0ff00000U, 0x0c500000U }, + { "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv", PVM_A32_OP_LDC, 0x0e100000U, 0x0c100000U }, + { "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv", PVM_A32_OP_STC, 0x0e100000U, 0x0c000000U }, + { "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_ADC_IMM, 0x0fe00000U, 0x02a00000U }, + { "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_ADC_REG, 0x0fe00010U, 0x00a00000U }, + { "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm", PVM_A32_OP_ADC_RSR, 0x0fe00090U, 0x00a00010U }, + { "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_ADD_IMM, 0x0fe00000U, 0x02800000U }, + { "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_ADD_REG, 0x0fe00010U, 0x00800000U }, + { "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm", PVM_A32_OP_ADD_RSR, 0x0fe00090U, 0x00800010U }, + { "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_AND_IMM, 0x0fe00000U, 0x02000000U }, + { "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_AND_REG, 0x0fe00010U, 0x00000000U }, + { "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm", PVM_A32_OP_AND_RSR, 0x0fe00090U, 0x00000010U }, + { "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_BIC_IMM, 0x0fe00000U, 0x03c00000U }, + { "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_BIC_REG, 0x0fe00010U, 0x01c00000U }, + { "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm", PVM_A32_OP_BIC_RSR, 0x0fe00090U, 0x01c00010U }, + { "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv", PVM_A32_OP_CMN_IMM, 0x0ff0f000U, 0x03700000U }, + { "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm", PVM_A32_OP_CMN_REG, 0x0ff0f010U, 0x01700000U }, + { "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm", PVM_A32_OP_CMN_RSR, 0x0ff0f090U, 0x01700010U }, + { "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv", PVM_A32_OP_CMP_IMM, 0x0ff0f000U, 0x03500000U }, + { "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm", PVM_A32_OP_CMP_REG, 0x0ff0f010U, 0x01500000U }, + { "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm", PVM_A32_OP_CMP_RSR, 0x0ff0f090U, 0x01500010U }, + { "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_EOR_IMM, 0x0fe00000U, 0x02200000U }, + { "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_EOR_REG, 0x0fe00010U, 0x00200000U }, + { "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm", PVM_A32_OP_EOR_RSR, 0x0fe00090U, 0x00200010U }, + { "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv", PVM_A32_OP_MOV_IMM, 0x0fef0000U, 0x03a00000U }, + { "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm", PVM_A32_OP_MOV_REG, 0x0fef0010U, 0x01a00000U }, + { "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm", PVM_A32_OP_MOV_RSR, 0x0fef0090U, 0x01a00010U }, + { "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv", PVM_A32_OP_MVN_IMM, 0x0fef0000U, 0x03e00000U }, + { "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm", PVM_A32_OP_MVN_REG, 0x0fef0010U, 0x01e00000U }, + { "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm", PVM_A32_OP_MVN_RSR, 0x0fef0090U, 0x01e00010U }, + { "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_ORR_IMM, 0x0fe00000U, 0x03800000U }, + { "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_ORR_REG, 0x0fe00010U, 0x01800000U }, + { "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm", PVM_A32_OP_ORR_RSR, 0x0fe00090U, 0x01800010U }, + { "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_RSB_IMM, 0x0fe00000U, 0x02600000U }, + { "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_RSB_REG, 0x0fe00010U, 0x00600000U }, + { "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm", PVM_A32_OP_RSB_RSR, 0x0fe00090U, 0x00600010U }, + { "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_RSC_IMM, 0x0fe00000U, 0x02e00000U }, + { "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_RSC_REG, 0x0fe00010U, 0x00e00000U }, + { "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm", PVM_A32_OP_RSC_RSR, 0x0fe00090U, 0x00e00010U }, + { "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_SBC_IMM, 0x0fe00000U, 0x02c00000U }, + { "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_SBC_REG, 0x0fe00010U, 0x00c00000U }, + { "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm", PVM_A32_OP_SBC_RSR, 0x0fe00090U, 0x00c00010U }, + { "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_SUB_IMM, 0x0fe00000U, 0x02400000U }, + { "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_SUB_REG, 0x0fe00010U, 0x00400000U }, + { "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm", PVM_A32_OP_SUB_RSR, 0x0fe00090U, 0x00400010U }, + { "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv", PVM_A32_OP_TEQ_IMM, 0x0ff0f000U, 0x03300000U }, + { "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm", PVM_A32_OP_TEQ_REG, 0x0ff0f010U, 0x01300000U }, + { "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm", PVM_A32_OP_TEQ_RSR, 0x0ff0f090U, 0x01300010U }, + { "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv", PVM_A32_OP_TST_IMM, 0x0ff0f000U, 0x03100000U }, + { "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm", PVM_A32_OP_TST_REG, 0x0ff0f010U, 0x01100000U }, + { "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm", PVM_A32_OP_TST_RSR, 0x0ff0f090U, 0x01100010U }, + { "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv", PVM_A32_OP_BKPT, 0x0ff000f0U, 0x01200070U }, + { "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_SVC, 0x0f000000U, 0x0f000000U }, + { "UDF", "111001111111------------1111----", PVM_A32_OP_UDF, 0xfff000f0U, 0xe7f000f0U }, + { "SXTB", "cccc011010101111ddddrr000111mmmm", PVM_A32_OP_SXTB, 0x0fff03f0U, 0x06af0070U }, + { "SXTB16", "cccc011010001111ddddrr000111mmmm", PVM_A32_OP_SXTB16, 0x0fff03f0U, 0x068f0070U }, + { "SXTH", "cccc011010111111ddddrr000111mmmm", PVM_A32_OP_SXTH, 0x0fff03f0U, 0x06bf0070U }, + { "SXTAB", "cccc01101010nnnnddddrr000111mmmm", PVM_A32_OP_SXTAB, 0x0ff003f0U, 0x06a00070U }, + { "SXTAB16", "cccc01101000nnnnddddrr000111mmmm", PVM_A32_OP_SXTAB16, 0x0ff003f0U, 0x06800070U }, + { "SXTAH", "cccc01101011nnnnddddrr000111mmmm", PVM_A32_OP_SXTAH, 0x0ff003f0U, 0x06b00070U }, + { "UXTB", "cccc011011101111ddddrr000111mmmm", PVM_A32_OP_UXTB, 0x0fff03f0U, 0x06ef0070U }, + { "UXTB16", "cccc011011001111ddddrr000111mmmm", PVM_A32_OP_UXTB16, 0x0fff03f0U, 0x06cf0070U }, + { "UXTH", "cccc011011111111ddddrr000111mmmm", PVM_A32_OP_UXTH, 0x0fff03f0U, 0x06ff0070U }, + { "UXTAB", "cccc01101110nnnnddddrr000111mmmm", PVM_A32_OP_UXTAB, 0x0ff003f0U, 0x06e00070U }, + { "UXTAB16", "cccc01101100nnnnddddrr000111mmmm", PVM_A32_OP_UXTAB16, 0x0ff003f0U, 0x06c00070U }, + { "UXTAH", "cccc01101111nnnnddddrr000111mmmm", PVM_A32_OP_UXTAH, 0x0ff003f0U, 0x06f00070U }, + { "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii", PVM_A32_OP_PLD_IMM, 0xff30f000U, 0xf510f000U }, + { "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm", PVM_A32_OP_PLD_REG, 0xff30f010U, 0xf710f000U }, + { "SEV", "----0011001000001111000000000100", PVM_A32_OP_SEV, 0x0fffffffU, 0x0320f004U }, + { "SEVL", "----0011001000001111000000000101", PVM_A32_OP_SEVL, 0x0fffffffU, 0x0320f005U }, + { "WFE", "----0011001000001111000000000010", PVM_A32_OP_WFE, 0x0fffffffU, 0x0320f002U }, + { "WFI", "----0011001000001111000000000011", PVM_A32_OP_WFI, 0x0fffffffU, 0x0320f003U }, + { "YIELD", "----0011001000001111000000000001", PVM_A32_OP_YIELD, 0x0fffffffU, 0x0320f001U }, + { "NOP", "----0011001000001111000000000000", PVM_A32_OP_NOP, 0x0fffffffU, 0x0320f000U }, + { "CLREX", "11110101011111111111000000011111", PVM_A32_OP_CLREX, 0xffffffffU, 0xf57ff01fU }, + { "SWP", "cccc00010000nnnntttt00001001uuuu", PVM_A32_OP_SWP, 0x0ff00ff0U, 0x01000090U }, + { "SWPB", "cccc00010100nnnntttt00001001uuuu", PVM_A32_OP_SWPB, 0x0ff00ff0U, 0x01400090U }, + { "STL", "cccc00011000nnnn111111001001tttt", PVM_A32_OP_STL, 0x0ff0fff0U, 0x0180fc90U }, + { "STLEX", "cccc00011000nnnndddd11101001tttt", PVM_A32_OP_STLEX, 0x0ff00ff0U, 0x01800e90U }, + { "STREX", "cccc00011000nnnndddd11111001mmmm", PVM_A32_OP_STREX, 0x0ff00ff0U, 0x01800f90U }, + { "LDA", "cccc00011001nnnndddd110010011111", PVM_A32_OP_LDA, 0x0ff00fffU, 0x01900c9fU }, + { "LDAEX", "cccc00011001nnnndddd111010011111", PVM_A32_OP_LDAEX, 0x0ff00fffU, 0x01900e9fU }, + { "LDREX", "cccc00011001nnnndddd111110011111", PVM_A32_OP_LDREX, 0x0ff00fffU, 0x01900f9fU }, + { "STLEXD", "cccc00011010nnnndddd11101001mmmm", PVM_A32_OP_STLEXD, 0x0ff00ff0U, 0x01a00e90U }, + { "STREXD", "cccc00011010nnnndddd11111001mmmm", PVM_A32_OP_STREXD, 0x0ff00ff0U, 0x01a00f90U }, + { "LDAEXD", "cccc00011011nnnndddd111010011111", PVM_A32_OP_LDAEXD, 0x0ff00fffU, 0x01b00e9fU }, + { "LDREXD", "cccc00011011nnnndddd111110011111", PVM_A32_OP_LDREXD, 0x0ff00fffU, 0x01b00f9fU }, + { "STLB", "cccc00011100nnnn111111001001tttt", PVM_A32_OP_STLB, 0x0ff0fff0U, 0x01c0fc90U }, + { "STLEXB", "cccc00011100nnnndddd11101001mmmm", PVM_A32_OP_STLEXB, 0x0ff00ff0U, 0x01c00e90U }, + { "STREXB", "cccc00011100nnnndddd11111001mmmm", PVM_A32_OP_STREXB, 0x0ff00ff0U, 0x01c00f90U }, + { "LDAB", "cccc00011101nnnndddd110010011111", PVM_A32_OP_LDAB, 0x0ff00fffU, 0x01d00c9fU }, + { "LDAEXB", "cccc00011101nnnndddd111010011111", PVM_A32_OP_LDAEXB, 0x0ff00fffU, 0x01d00e9fU }, + { "LDREXB", "cccc00011101nnnndddd111110011111", PVM_A32_OP_LDREXB, 0x0ff00fffU, 0x01d00f9fU }, + { "STLH", "cccc00011110nnnn111111001001mmmm", PVM_A32_OP_STLH, 0x0ff0fff0U, 0x01e0fc90U }, + { "STLEXH", "cccc00011110nnnndddd11101001mmmm", PVM_A32_OP_STLEXH, 0x0ff00ff0U, 0x01e00e90U }, + { "STREXH", "cccc00011110nnnndddd11111001mmmm", PVM_A32_OP_STREXH, 0x0ff00ff0U, 0x01e00f90U }, + { "LDAH", "cccc00011111nnnndddd110010011111", PVM_A32_OP_LDAH, 0x0ff00fffU, 0x01f00c9fU }, + { "LDAEXH", "cccc00011111nnnndddd111010011111", PVM_A32_OP_LDAEXH, 0x0ff00fffU, 0x01f00e9fU }, + { "LDREXH", "cccc00011111nnnndddd111110011111", PVM_A32_OP_LDREXH, 0x0ff00fffU, 0x01f00f9fU }, + { "LDRBT (A1)", "----0100-111--------------------", PVM_A32_OP_LDRBT, 0x0f700000U, 0x04700000U }, + { "LDRBT (A2)", "----0110-111---------------0----", PVM_A32_OP_LDRBT, 0x0f700010U, 0x06700000U }, + { "LDRHT (A1)", "----0000-111------------1011----", PVM_A32_OP_LDRHT, 0x0f7000f0U, 0x007000b0U }, + { "LDRHT (A1)", "----0000-1111111--------1011----", PVM_A32_OP_LDRHT, 0x0f7f00f0U, 0x007f00b0U }, + { "LDRHT (A2)", "----0000-011--------00001011----", PVM_A32_OP_LDRHT, 0x0f700ff0U, 0x003000b0U }, + { "LDRSBT (A1)", "----0000-111------------1101----", PVM_A32_OP_LDRSBT, 0x0f7000f0U, 0x007000d0U }, + { "LDRSBT (A2)", "----0000-011--------00001101----", PVM_A32_OP_LDRSBT, 0x0f700ff0U, 0x003000d0U }, + { "LDRSHT (A1)", "----0000-111------------1111----", PVM_A32_OP_LDRSHT, 0x0f7000f0U, 0x007000f0U }, + { "LDRSHT (A2)", "----0000-011--------00001111----", PVM_A32_OP_LDRSHT, 0x0f700ff0U, 0x003000f0U }, + { "LDRT (A1)", "----0100-011--------------------", PVM_A32_OP_LDRT, 0x0f700000U, 0x04300000U }, + { "LDRT (A2)", "----0110-011---------------0----", PVM_A32_OP_LDRT, 0x0f700010U, 0x06300000U }, + { "STRBT (A1)", "----0100-110--------------------", PVM_A32_OP_STRBT, 0x0f700000U, 0x04600000U }, + { "STRBT (A2)", "----0110-110---------------0----", PVM_A32_OP_STRBT, 0x0f700010U, 0x06600000U }, + { "STRHT (A1)", "----0000-110------------1011----", PVM_A32_OP_STRHT, 0x0f7000f0U, 0x006000b0U }, + { "STRHT (A2)", "----0000-010--------00001011----", PVM_A32_OP_STRHT, 0x0f700ff0U, 0x002000b0U }, + { "STRT (A1)", "----0100-010--------------------", PVM_A32_OP_STRT, 0x0f700000U, 0x04200000U }, + { "STRT (A2)", "----0110-010---------------0----", PVM_A32_OP_STRT, 0x0f700010U, 0x06200000U }, + { "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv", PVM_A32_OP_LDR_LIT, 0x0f7f0000U, 0x051f0000U }, + { "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv", PVM_A32_OP_LDR_IMM, 0x0e500000U, 0x04100000U }, + { "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm", PVM_A32_OP_LDR_REG, 0x0e500010U, 0x06100000U }, + { "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv", PVM_A32_OP_LDRB_LIT, 0x0f7f0000U, 0x055f0000U }, + { "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv", PVM_A32_OP_LDRB_IMM, 0x0e500000U, 0x04500000U }, + { "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm", PVM_A32_OP_LDRB_REG, 0x0e500010U, 0x06500000U }, + { "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv", PVM_A32_OP_LDRD_LIT, 0x0f7f00f0U, 0x014f00d0U }, + { "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv", PVM_A32_OP_LDRD_IMM, 0x0e5000f0U, 0x004000d0U }, + { "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm", PVM_A32_OP_LDRD_REG, 0x0e500ff0U, 0x000000d0U }, + { "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv", PVM_A32_OP_LDRH_LIT, 0x0e5f00f0U, 0x005f00b0U }, + { "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv", PVM_A32_OP_LDRH_IMM, 0x0e5000f0U, 0x005000b0U }, + { "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm", PVM_A32_OP_LDRH_REG, 0x0e500ff0U, 0x001000b0U }, + { "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv", PVM_A32_OP_LDRSB_LIT, 0x0f7f00f0U, 0x015f00d0U }, + { "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv", PVM_A32_OP_LDRSB_IMM, 0x0e5000f0U, 0x005000d0U }, + { "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm", PVM_A32_OP_LDRSB_REG, 0x0e500ff0U, 0x001000d0U }, + { "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv", PVM_A32_OP_LDRSH_LIT, 0x0f7f00f0U, 0x015f00f0U }, + { "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv", PVM_A32_OP_LDRSH_IMM, 0x0e5000f0U, 0x005000f0U }, + { "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm", PVM_A32_OP_LDRSH_REG, 0x0e500ff0U, 0x001000f0U }, + { "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv", PVM_A32_OP_STR_IMM, 0x0e500000U, 0x04000000U }, + { "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm", PVM_A32_OP_STR_REG, 0x0e500010U, 0x06000000U }, + { "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv", PVM_A32_OP_STRB_IMM, 0x0e500000U, 0x04400000U }, + { "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm", PVM_A32_OP_STRB_REG, 0x0e500010U, 0x06400000U }, + { "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv", PVM_A32_OP_STRD_IMM, 0x0e5000f0U, 0x004000f0U }, + { "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm", PVM_A32_OP_STRD_REG, 0x0e500ff0U, 0x000000f0U }, + { "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv", PVM_A32_OP_STRH_IMM, 0x0e5000f0U, 0x004000b0U }, + { "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm", PVM_A32_OP_STRH_REG, 0x0e500ff0U, 0x000000b0U }, + { "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDM, 0x0fd00000U, 0x08900000U }, + { "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDMDA, 0x0fd00000U, 0x08100000U }, + { "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDMDB, 0x0fd00000U, 0x09100000U }, + { "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDMIB, 0x0fd00000U, 0x09900000U }, + { "LDM (usr reg)", "----100--101----0---------------", PVM_A32_OP_LDM_USR, 0x0e708000U, 0x08500000U }, + { "LDM (exce ret)", "----100--1-1----1---------------", PVM_A32_OP_LDM_ERET, 0x0e508000U, 0x08508000U }, + { "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STM, 0x0fd00000U, 0x08800000U }, + { "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STMDA, 0x0fd00000U, 0x08000000U }, + { "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STMDB, 0x0fd00000U, 0x09000000U }, + { "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STMIB, 0x0fd00000U, 0x09800000U }, + { "STM (usr reg)", "----100--100--------------------", PVM_A32_OP_STM_USR, 0x0e700000U, 0x08400000U }, + { "BFC", "cccc0111110vvvvvddddvvvvv0011111", PVM_A32_OP_BFC, 0x0fe0007fU, 0x07c0001fU }, + { "BFI", "cccc0111110vvvvvddddvvvvv001nnnn", PVM_A32_OP_BFI, 0x0fe00070U, 0x07c00010U }, + { "CLZ", "cccc000101101111dddd11110001mmmm", PVM_A32_OP_CLZ, 0x0fff0ff0U, 0x016f0f10U }, + { "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv", PVM_A32_OP_MOVT, 0x0ff00000U, 0x03400000U }, + { "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv", PVM_A32_OP_MOVW, 0x0ff00000U, 0x03000000U }, + { "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn", PVM_A32_OP_SBFX, 0x0fe00070U, 0x07a00050U }, + { "SEL", "cccc01101000nnnndddd11111011mmmm", PVM_A32_OP_SEL, 0x0ff00ff0U, 0x06800fb0U }, + { "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn", PVM_A32_OP_UBFX, 0x0fe00070U, 0x07e00050U }, + { "USAD8", "cccc01111000dddd1111mmmm0001nnnn", PVM_A32_OP_USAD8, 0x0ff0f0f0U, 0x0780f010U }, + { "USADA8", "cccc01111000ddddaaaammmm0001nnnn", PVM_A32_OP_USADA8, 0x0ff000f0U, 0x07800010U }, + { "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm", PVM_A32_OP_PKHBT, 0x0ff00070U, 0x06800010U }, + { "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm", PVM_A32_OP_PKHTB, 0x0ff00070U, 0x06800050U }, + { "RBIT", "cccc011011111111dddd11110011mmmm", PVM_A32_OP_RBIT, 0x0fff0ff0U, 0x06ff0f30U }, + { "REV", "cccc011010111111dddd11110011mmmm", PVM_A32_OP_REV, 0x0fff0ff0U, 0x06bf0f30U }, + { "REV16", "cccc011010111111dddd11111011mmmm", PVM_A32_OP_REV16, 0x0fff0ff0U, 0x06bf0fb0U }, + { "REVSH", "cccc011011111111dddd11111011mmmm", PVM_A32_OP_REVSH, 0x0fff0ff0U, 0x06ff0fb0U }, + { "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn", PVM_A32_OP_SSAT, 0x0fe00030U, 0x06a00010U }, + { "SSAT16", "cccc01101010vvvvdddd11110011nnnn", PVM_A32_OP_SSAT16, 0x0ff00ff0U, 0x06a00f30U }, + { "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn", PVM_A32_OP_USAT, 0x0fe00030U, 0x06e00010U }, + { "USAT16", "cccc01101110vvvvdddd11110011nnnn", PVM_A32_OP_USAT16, 0x0ff00ff0U, 0x06e00f30U }, + { "SDIV", "cccc01110001dddd1111mmmm0001nnnn", PVM_A32_OP_SDIV, 0x0ff0f0f0U, 0x0710f010U }, + { "UDIV", "cccc01110011dddd1111mmmm0001nnnn", PVM_A32_OP_UDIV, 0x0ff0f0f0U, 0x0730f010U }, + { "MLA", "cccc0000001Sddddaaaammmm1001nnnn", PVM_A32_OP_MLA, 0x0fe000f0U, 0x00200090U }, + { "MLS", "cccc00000110ddddaaaammmm1001nnnn", PVM_A32_OP_MLS, 0x0ff000f0U, 0x00600090U }, + { "MUL", "cccc0000000Sdddd0000mmmm1001nnnn", PVM_A32_OP_MUL, 0x0fe0f0f0U, 0x00000090U }, + { "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn", PVM_A32_OP_SMLAL, 0x0fe000f0U, 0x00e00090U }, + { "SMULL", "cccc0000110Sddddaaaammmm1001nnnn", PVM_A32_OP_SMULL, 0x0fe000f0U, 0x00c00090U }, + { "UMAAL", "cccc00000100ddddaaaammmm1001nnnn", PVM_A32_OP_UMAAL, 0x0ff000f0U, 0x00400090U }, + { "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn", PVM_A32_OP_UMLAL, 0x0fe000f0U, 0x00a00090U }, + { "UMULL", "cccc0000100Sddddaaaammmm1001nnnn", PVM_A32_OP_UMULL, 0x0fe000f0U, 0x00800090U }, + { "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn", PVM_A32_OP_SMLALXY, 0x0ff00090U, 0x01400080U }, + { "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn", PVM_A32_OP_SMLAXY, 0x0ff00090U, 0x01000080U }, + { "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn", PVM_A32_OP_SMULXY, 0x0ff0f090U, 0x01600080U }, + { "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn", PVM_A32_OP_SMLAWY, 0x0ff000b0U, 0x01200080U }, + { "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn", PVM_A32_OP_SMULWY, 0x0ff0f0b0U, 0x012000a0U }, + { "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn", PVM_A32_OP_SMMUL, 0x0ff0f0d0U, 0x0750f010U }, + { "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn", PVM_A32_OP_SMMLA, 0x0ff000d0U, 0x07500010U }, + { "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn", PVM_A32_OP_SMMLS, 0x0ff000d0U, 0x075000d0U }, + { "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn", PVM_A32_OP_SMUAD, 0x0ff0f0d0U, 0x0700f010U }, + { "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn", PVM_A32_OP_SMLAD, 0x0ff000d0U, 0x07000010U }, + { "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn", PVM_A32_OP_SMLALD, 0x0ff000d0U, 0x07400010U }, + { "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn", PVM_A32_OP_SMUSD, 0x0ff0f0d0U, 0x0700f050U }, + { "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn", PVM_A32_OP_SMLSD, 0x0ff000d0U, 0x07000050U }, + { "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn", PVM_A32_OP_SMLSLD, 0x0ff000d0U, 0x07400050U }, + { "SADD8", "cccc01100001nnnndddd11111001mmmm", PVM_A32_OP_SADD8, 0x0ff00ff0U, 0x06100f90U }, + { "SADD16", "cccc01100001nnnndddd11110001mmmm", PVM_A32_OP_SADD16, 0x0ff00ff0U, 0x06100f10U }, + { "SASX", "cccc01100001nnnndddd11110011mmmm", PVM_A32_OP_SASX, 0x0ff00ff0U, 0x06100f30U }, + { "SSAX", "cccc01100001nnnndddd11110101mmmm", PVM_A32_OP_SSAX, 0x0ff00ff0U, 0x06100f50U }, + { "SSUB8", "cccc01100001nnnndddd11111111mmmm", PVM_A32_OP_SSUB8, 0x0ff00ff0U, 0x06100ff0U }, + { "SSUB16", "cccc01100001nnnndddd11110111mmmm", PVM_A32_OP_SSUB16, 0x0ff00ff0U, 0x06100f70U }, + { "UADD8", "cccc01100101nnnndddd11111001mmmm", PVM_A32_OP_UADD8, 0x0ff00ff0U, 0x06500f90U }, + { "UADD16", "cccc01100101nnnndddd11110001mmmm", PVM_A32_OP_UADD16, 0x0ff00ff0U, 0x06500f10U }, + { "UASX", "cccc01100101nnnndddd11110011mmmm", PVM_A32_OP_UASX, 0x0ff00ff0U, 0x06500f30U }, + { "USAX", "cccc01100101nnnndddd11110101mmmm", PVM_A32_OP_USAX, 0x0ff00ff0U, 0x06500f50U }, + { "USUB8", "cccc01100101nnnndddd11111111mmmm", PVM_A32_OP_USUB8, 0x0ff00ff0U, 0x06500ff0U }, + { "USUB16", "cccc01100101nnnndddd11110111mmmm", PVM_A32_OP_USUB16, 0x0ff00ff0U, 0x06500f70U }, + { "QADD8", "cccc01100010nnnndddd11111001mmmm", PVM_A32_OP_QADD8, 0x0ff00ff0U, 0x06200f90U }, + { "QADD16", "cccc01100010nnnndddd11110001mmmm", PVM_A32_OP_QADD16, 0x0ff00ff0U, 0x06200f10U }, + { "QASX", "cccc01100010nnnndddd11110011mmmm", PVM_A32_OP_QASX, 0x0ff00ff0U, 0x06200f30U }, + { "QSAX", "cccc01100010nnnndddd11110101mmmm", PVM_A32_OP_QSAX, 0x0ff00ff0U, 0x06200f50U }, + { "QSUB8", "cccc01100010nnnndddd11111111mmmm", PVM_A32_OP_QSUB8, 0x0ff00ff0U, 0x06200ff0U }, + { "QSUB16", "cccc01100010nnnndddd11110111mmmm", PVM_A32_OP_QSUB16, 0x0ff00ff0U, 0x06200f70U }, + { "UQADD8", "cccc01100110nnnndddd11111001mmmm", PVM_A32_OP_UQADD8, 0x0ff00ff0U, 0x06600f90U }, + { "UQADD16", "cccc01100110nnnndddd11110001mmmm", PVM_A32_OP_UQADD16, 0x0ff00ff0U, 0x06600f10U }, + { "UQASX", "cccc01100110nnnndddd11110011mmmm", PVM_A32_OP_UQASX, 0x0ff00ff0U, 0x06600f30U }, + { "UQSAX", "cccc01100110nnnndddd11110101mmmm", PVM_A32_OP_UQSAX, 0x0ff00ff0U, 0x06600f50U }, + { "UQSUB8", "cccc01100110nnnndddd11111111mmmm", PVM_A32_OP_UQSUB8, 0x0ff00ff0U, 0x06600ff0U }, + { "UQSUB16", "cccc01100110nnnndddd11110111mmmm", PVM_A32_OP_UQSUB16, 0x0ff00ff0U, 0x06600f70U }, + { "SHADD8", "cccc01100011nnnndddd11111001mmmm", PVM_A32_OP_SHADD8, 0x0ff00ff0U, 0x06300f90U }, + { "SHADD16", "cccc01100011nnnndddd11110001mmmm", PVM_A32_OP_SHADD16, 0x0ff00ff0U, 0x06300f10U }, + { "SHASX", "cccc01100011nnnndddd11110011mmmm", PVM_A32_OP_SHASX, 0x0ff00ff0U, 0x06300f30U }, + { "SHSAX", "cccc01100011nnnndddd11110101mmmm", PVM_A32_OP_SHSAX, 0x0ff00ff0U, 0x06300f50U }, + { "SHSUB8", "cccc01100011nnnndddd11111111mmmm", PVM_A32_OP_SHSUB8, 0x0ff00ff0U, 0x06300ff0U }, + { "SHSUB16", "cccc01100011nnnndddd11110111mmmm", PVM_A32_OP_SHSUB16, 0x0ff00ff0U, 0x06300f70U }, + { "UHADD8", "cccc01100111nnnndddd11111001mmmm", PVM_A32_OP_UHADD8, 0x0ff00ff0U, 0x06700f90U }, + { "UHADD16", "cccc01100111nnnndddd11110001mmmm", PVM_A32_OP_UHADD16, 0x0ff00ff0U, 0x06700f10U }, + { "UHASX", "cccc01100111nnnndddd11110011mmmm", PVM_A32_OP_UHASX, 0x0ff00ff0U, 0x06700f30U }, + { "UHSAX", "cccc01100111nnnndddd11110101mmmm", PVM_A32_OP_UHSAX, 0x0ff00ff0U, 0x06700f50U }, + { "UHSUB8", "cccc01100111nnnndddd11111111mmmm", PVM_A32_OP_UHSUB8, 0x0ff00ff0U, 0x06700ff0U }, + { "UHSUB16", "cccc01100111nnnndddd11110111mmmm", PVM_A32_OP_UHSUB16, 0x0ff00ff0U, 0x06700f70U }, + { "QADD", "cccc00010000nnnndddd00000101mmmm", PVM_A32_OP_QADD, 0x0ff00ff0U, 0x01000050U }, + { "QSUB", "cccc00010010nnnndddd00000101mmmm", PVM_A32_OP_QSUB, 0x0ff00ff0U, 0x01200050U }, + { "QDADD", "cccc00010100nnnndddd00000101mmmm", PVM_A32_OP_QDADD, 0x0ff00ff0U, 0x01400050U }, + { "QDSUB", "cccc00010110nnnndddd00000101mmmm", PVM_A32_OP_QDSUB, 0x0ff00ff0U, 0x01600050U }, + { "MRS", "cccc000100001111dddd000000000000", PVM_A32_OP_MRS, 0x0fff0fffU, 0x010f0000U }, + { "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv", PVM_A32_OP_MSR_IMM, 0x0ff0f000U, 0x0320f000U }, + { "MSR (reg)", "cccc00010010mmmm111100000000nnnn", PVM_A32_OP_MSR_REG, 0x0ff0fff0U, 0x0120f000U }, }; - const decode_bucket_t g_decoder_lookup_table[4096] = { [0x000] = { .instructions = { &g_instructions[29], }, .count = 1U }, [0x001] = { .instructions = { &g_instructions[30], }, .count = 1U }, diff --git a/src/jit/frontend/decoder/arm32_table_generated.h b/src/jit/frontend/decoder/arm32_table.h similarity index 79% rename from src/jit/frontend/decoder/arm32_table_generated.h rename to src/jit/frontend/decoder/arm32_table.h index 75e15fc..7cbc6a8 100644 --- a/src/jit/frontend/decoder/arm32_table_generated.h +++ b/src/jit/frontend/decoder/arm32_table.h @@ -1,3 +1,5 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* This file is generated by scripts/generate_jit_assets.py */ #ifndef POUND_JIT_DECODER_ARM32_GENERATED_H #define POUND_JIT_DECODER_ARM32_GENERATED_H diff --git a/src/jit/interpreter/a32/instruction.c b/src/jit/interpreter/a32/instruction.c deleted file mode 100644 index 626d743..0000000 --- a/src/jit/interpreter/a32/instruction.c +++ /dev/null @@ -1,3 +0,0 @@ -/* - * Defines pvm_jit_interpreter_instruction_t struct and its internal opcodes. - */ diff --git a/src/jit/interpreter/arm32/handler_table.inc b/src/jit/interpreter/arm32/handler_table.inc new file mode 100644 index 0000000..6c6b528 --- /dev/null +++ b/src/jit/interpreter/arm32/handler_table.inc @@ -0,0 +1,252 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* This file is generated by scripts/generate_jit_assets.py */ + [PVM_A32_OP_DMB] = &&HANDLER_PVM_A32_OP_DMB, + [PVM_A32_OP_DSB] = &&HANDLER_PVM_A32_OP_DSB, + [PVM_A32_OP_ISB] = &&HANDLER_PVM_A32_OP_ISB, + [PVM_A32_OP_BLX_IMM] = &&HANDLER_PVM_A32_OP_BLX_IMM, + [PVM_A32_OP_BLX_REG] = &&HANDLER_PVM_A32_OP_BLX_REG, + [PVM_A32_OP_B] = &&HANDLER_PVM_A32_OP_B, + [PVM_A32_OP_BL] = &&HANDLER_PVM_A32_OP_BL, + [PVM_A32_OP_BX] = &&HANDLER_PVM_A32_OP_BX, + [PVM_A32_OP_BXJ] = &&HANDLER_PVM_A32_OP_BXJ, + [PVM_A32_OP_RFE] = &&HANDLER_PVM_A32_OP_RFE, + [PVM_A32_OP_SRS] = &&HANDLER_PVM_A32_OP_SRS, + [PVM_A32_OP_CPS] = &&HANDLER_PVM_A32_OP_CPS, + [PVM_A32_OP_SETEND] = &&HANDLER_PVM_A32_OP_SETEND, + [PVM_A32_OP_CRC32] = &&HANDLER_PVM_A32_OP_CRC32, + [PVM_A32_OP_CRC32C] = &&HANDLER_PVM_A32_OP_CRC32C, + [PVM_A32_OP_CDP] = &&HANDLER_PVM_A32_OP_CDP, + [PVM_A32_OP_MCR] = &&HANDLER_PVM_A32_OP_MCR, + [PVM_A32_OP_MCRR] = &&HANDLER_PVM_A32_OP_MCRR, + [PVM_A32_OP_MRC] = &&HANDLER_PVM_A32_OP_MRC, + [PVM_A32_OP_MRRC] = &&HANDLER_PVM_A32_OP_MRRC, + [PVM_A32_OP_LDC] = &&HANDLER_PVM_A32_OP_LDC, + [PVM_A32_OP_STC] = &&HANDLER_PVM_A32_OP_STC, + [PVM_A32_OP_ADC_IMM] = &&HANDLER_PVM_A32_OP_ADC_IMM, + [PVM_A32_OP_ADC_REG] = &&HANDLER_PVM_A32_OP_ADC_REG, + [PVM_A32_OP_ADC_RSR] = &&HANDLER_PVM_A32_OP_ADC_RSR, + [PVM_A32_OP_ADD_IMM] = &&HANDLER_PVM_A32_OP_ADD_IMM, + [PVM_A32_OP_ADD_REG] = &&HANDLER_PVM_A32_OP_ADD_REG, + [PVM_A32_OP_ADD_RSR] = &&HANDLER_PVM_A32_OP_ADD_RSR, + [PVM_A32_OP_AND_IMM] = &&HANDLER_PVM_A32_OP_AND_IMM, + [PVM_A32_OP_AND_REG] = &&HANDLER_PVM_A32_OP_AND_REG, + [PVM_A32_OP_AND_RSR] = &&HANDLER_PVM_A32_OP_AND_RSR, + [PVM_A32_OP_BIC_IMM] = &&HANDLER_PVM_A32_OP_BIC_IMM, + [PVM_A32_OP_BIC_REG] = &&HANDLER_PVM_A32_OP_BIC_REG, + [PVM_A32_OP_BIC_RSR] = &&HANDLER_PVM_A32_OP_BIC_RSR, + [PVM_A32_OP_CMN_IMM] = &&HANDLER_PVM_A32_OP_CMN_IMM, + [PVM_A32_OP_CMN_REG] = &&HANDLER_PVM_A32_OP_CMN_REG, + [PVM_A32_OP_CMN_RSR] = &&HANDLER_PVM_A32_OP_CMN_RSR, + [PVM_A32_OP_CMP_IMM] = &&HANDLER_PVM_A32_OP_CMP_IMM, + [PVM_A32_OP_CMP_REG] = &&HANDLER_PVM_A32_OP_CMP_REG, + [PVM_A32_OP_CMP_RSR] = &&HANDLER_PVM_A32_OP_CMP_RSR, + [PVM_A32_OP_EOR_IMM] = &&HANDLER_PVM_A32_OP_EOR_IMM, + [PVM_A32_OP_EOR_REG] = &&HANDLER_PVM_A32_OP_EOR_REG, + [PVM_A32_OP_EOR_RSR] = &&HANDLER_PVM_A32_OP_EOR_RSR, + [PVM_A32_OP_MOV_IMM] = &&HANDLER_PVM_A32_OP_MOV_IMM, + [PVM_A32_OP_MOV_REG] = &&HANDLER_PVM_A32_OP_MOV_REG, + [PVM_A32_OP_MOV_RSR] = &&HANDLER_PVM_A32_OP_MOV_RSR, + [PVM_A32_OP_MVN_IMM] = &&HANDLER_PVM_A32_OP_MVN_IMM, + [PVM_A32_OP_MVN_REG] = &&HANDLER_PVM_A32_OP_MVN_REG, + [PVM_A32_OP_MVN_RSR] = &&HANDLER_PVM_A32_OP_MVN_RSR, + [PVM_A32_OP_ORR_IMM] = &&HANDLER_PVM_A32_OP_ORR_IMM, + [PVM_A32_OP_ORR_REG] = &&HANDLER_PVM_A32_OP_ORR_REG, + [PVM_A32_OP_ORR_RSR] = &&HANDLER_PVM_A32_OP_ORR_RSR, + [PVM_A32_OP_RSB_IMM] = &&HANDLER_PVM_A32_OP_RSB_IMM, + [PVM_A32_OP_RSB_REG] = &&HANDLER_PVM_A32_OP_RSB_REG, + [PVM_A32_OP_RSB_RSR] = &&HANDLER_PVM_A32_OP_RSB_RSR, + [PVM_A32_OP_RSC_IMM] = &&HANDLER_PVM_A32_OP_RSC_IMM, + [PVM_A32_OP_RSC_REG] = &&HANDLER_PVM_A32_OP_RSC_REG, + [PVM_A32_OP_RSC_RSR] = &&HANDLER_PVM_A32_OP_RSC_RSR, + [PVM_A32_OP_SBC_IMM] = &&HANDLER_PVM_A32_OP_SBC_IMM, + [PVM_A32_OP_SBC_REG] = &&HANDLER_PVM_A32_OP_SBC_REG, + [PVM_A32_OP_SBC_RSR] = &&HANDLER_PVM_A32_OP_SBC_RSR, + [PVM_A32_OP_SUB_IMM] = &&HANDLER_PVM_A32_OP_SUB_IMM, + [PVM_A32_OP_SUB_REG] = &&HANDLER_PVM_A32_OP_SUB_REG, + [PVM_A32_OP_SUB_RSR] = &&HANDLER_PVM_A32_OP_SUB_RSR, + [PVM_A32_OP_TEQ_IMM] = &&HANDLER_PVM_A32_OP_TEQ_IMM, + [PVM_A32_OP_TEQ_REG] = &&HANDLER_PVM_A32_OP_TEQ_REG, + [PVM_A32_OP_TEQ_RSR] = &&HANDLER_PVM_A32_OP_TEQ_RSR, + [PVM_A32_OP_TST_IMM] = &&HANDLER_PVM_A32_OP_TST_IMM, + [PVM_A32_OP_TST_REG] = &&HANDLER_PVM_A32_OP_TST_REG, + [PVM_A32_OP_TST_RSR] = &&HANDLER_PVM_A32_OP_TST_RSR, + [PVM_A32_OP_BKPT] = &&HANDLER_PVM_A32_OP_BKPT, + [PVM_A32_OP_SVC] = &&HANDLER_PVM_A32_OP_SVC, + [PVM_A32_OP_UDF] = &&HANDLER_PVM_A32_OP_UDF, + [PVM_A32_OP_SXTB] = &&HANDLER_PVM_A32_OP_SXTB, + [PVM_A32_OP_SXTB16] = &&HANDLER_PVM_A32_OP_SXTB16, + [PVM_A32_OP_SXTH] = &&HANDLER_PVM_A32_OP_SXTH, + [PVM_A32_OP_SXTAB] = &&HANDLER_PVM_A32_OP_SXTAB, + [PVM_A32_OP_SXTAB16] = &&HANDLER_PVM_A32_OP_SXTAB16, + [PVM_A32_OP_SXTAH] = &&HANDLER_PVM_A32_OP_SXTAH, + [PVM_A32_OP_UXTB] = &&HANDLER_PVM_A32_OP_UXTB, + [PVM_A32_OP_UXTB16] = &&HANDLER_PVM_A32_OP_UXTB16, + [PVM_A32_OP_UXTH] = &&HANDLER_PVM_A32_OP_UXTH, + [PVM_A32_OP_UXTAB] = &&HANDLER_PVM_A32_OP_UXTAB, + [PVM_A32_OP_UXTAB16] = &&HANDLER_PVM_A32_OP_UXTAB16, + [PVM_A32_OP_UXTAH] = &&HANDLER_PVM_A32_OP_UXTAH, + [PVM_A32_OP_PLD_IMM] = &&HANDLER_PVM_A32_OP_PLD_IMM, + [PVM_A32_OP_PLD_REG] = &&HANDLER_PVM_A32_OP_PLD_REG, + [PVM_A32_OP_SEV] = &&HANDLER_PVM_A32_OP_SEV, + [PVM_A32_OP_SEVL] = &&HANDLER_PVM_A32_OP_SEVL, + [PVM_A32_OP_WFE] = &&HANDLER_PVM_A32_OP_WFE, + [PVM_A32_OP_WFI] = &&HANDLER_PVM_A32_OP_WFI, + [PVM_A32_OP_YIELD] = &&HANDLER_PVM_A32_OP_YIELD, + [PVM_A32_OP_NOP] = &&HANDLER_PVM_A32_OP_NOP, + [PVM_A32_OP_CLREX] = &&HANDLER_PVM_A32_OP_CLREX, + [PVM_A32_OP_SWP] = &&HANDLER_PVM_A32_OP_SWP, + [PVM_A32_OP_SWPB] = &&HANDLER_PVM_A32_OP_SWPB, + [PVM_A32_OP_STL] = &&HANDLER_PVM_A32_OP_STL, + [PVM_A32_OP_STLEX] = &&HANDLER_PVM_A32_OP_STLEX, + [PVM_A32_OP_STREX] = &&HANDLER_PVM_A32_OP_STREX, + [PVM_A32_OP_LDA] = &&HANDLER_PVM_A32_OP_LDA, + [PVM_A32_OP_LDAEX] = &&HANDLER_PVM_A32_OP_LDAEX, + [PVM_A32_OP_LDREX] = &&HANDLER_PVM_A32_OP_LDREX, + [PVM_A32_OP_STLEXD] = &&HANDLER_PVM_A32_OP_STLEXD, + [PVM_A32_OP_STREXD] = &&HANDLER_PVM_A32_OP_STREXD, + [PVM_A32_OP_LDAEXD] = &&HANDLER_PVM_A32_OP_LDAEXD, + [PVM_A32_OP_LDREXD] = &&HANDLER_PVM_A32_OP_LDREXD, + [PVM_A32_OP_STLB] = &&HANDLER_PVM_A32_OP_STLB, + [PVM_A32_OP_STLEXB] = &&HANDLER_PVM_A32_OP_STLEXB, + [PVM_A32_OP_STREXB] = &&HANDLER_PVM_A32_OP_STREXB, + [PVM_A32_OP_LDAB] = &&HANDLER_PVM_A32_OP_LDAB, + [PVM_A32_OP_LDAEXB] = &&HANDLER_PVM_A32_OP_LDAEXB, + [PVM_A32_OP_LDREXB] = &&HANDLER_PVM_A32_OP_LDREXB, + [PVM_A32_OP_STLH] = &&HANDLER_PVM_A32_OP_STLH, + [PVM_A32_OP_STLEXH] = &&HANDLER_PVM_A32_OP_STLEXH, + [PVM_A32_OP_STREXH] = &&HANDLER_PVM_A32_OP_STREXH, + [PVM_A32_OP_LDAH] = &&HANDLER_PVM_A32_OP_LDAH, + [PVM_A32_OP_LDAEXH] = &&HANDLER_PVM_A32_OP_LDAEXH, + [PVM_A32_OP_LDREXH] = &&HANDLER_PVM_A32_OP_LDREXH, + [PVM_A32_OP_LDRBT] = &&HANDLER_PVM_A32_OP_LDRBT, + [PVM_A32_OP_LDRHT] = &&HANDLER_PVM_A32_OP_LDRHT, + [PVM_A32_OP_LDRSBT] = &&HANDLER_PVM_A32_OP_LDRSBT, + [PVM_A32_OP_LDRSHT] = &&HANDLER_PVM_A32_OP_LDRSHT, + [PVM_A32_OP_LDRT] = &&HANDLER_PVM_A32_OP_LDRT, + [PVM_A32_OP_STRBT] = &&HANDLER_PVM_A32_OP_STRBT, + [PVM_A32_OP_STRHT] = &&HANDLER_PVM_A32_OP_STRHT, + [PVM_A32_OP_STRT] = &&HANDLER_PVM_A32_OP_STRT, + [PVM_A32_OP_LDR_LIT] = &&HANDLER_PVM_A32_OP_LDR_LIT, + [PVM_A32_OP_LDR_IMM] = &&HANDLER_PVM_A32_OP_LDR_IMM, + [PVM_A32_OP_LDR_REG] = &&HANDLER_PVM_A32_OP_LDR_REG, + [PVM_A32_OP_LDRB_LIT] = &&HANDLER_PVM_A32_OP_LDRB_LIT, + [PVM_A32_OP_LDRB_IMM] = &&HANDLER_PVM_A32_OP_LDRB_IMM, + [PVM_A32_OP_LDRB_REG] = &&HANDLER_PVM_A32_OP_LDRB_REG, + [PVM_A32_OP_LDRD_LIT] = &&HANDLER_PVM_A32_OP_LDRD_LIT, + [PVM_A32_OP_LDRD_IMM] = &&HANDLER_PVM_A32_OP_LDRD_IMM, + [PVM_A32_OP_LDRD_REG] = &&HANDLER_PVM_A32_OP_LDRD_REG, + [PVM_A32_OP_LDRH_LIT] = &&HANDLER_PVM_A32_OP_LDRH_LIT, + [PVM_A32_OP_LDRH_IMM] = &&HANDLER_PVM_A32_OP_LDRH_IMM, + [PVM_A32_OP_LDRH_REG] = &&HANDLER_PVM_A32_OP_LDRH_REG, + [PVM_A32_OP_LDRSB_LIT] = &&HANDLER_PVM_A32_OP_LDRSB_LIT, + [PVM_A32_OP_LDRSB_IMM] = &&HANDLER_PVM_A32_OP_LDRSB_IMM, + [PVM_A32_OP_LDRSB_REG] = &&HANDLER_PVM_A32_OP_LDRSB_REG, + [PVM_A32_OP_LDRSH_LIT] = &&HANDLER_PVM_A32_OP_LDRSH_LIT, + [PVM_A32_OP_LDRSH_IMM] = &&HANDLER_PVM_A32_OP_LDRSH_IMM, + [PVM_A32_OP_LDRSH_REG] = &&HANDLER_PVM_A32_OP_LDRSH_REG, + [PVM_A32_OP_STR_IMM] = &&HANDLER_PVM_A32_OP_STR_IMM, + [PVM_A32_OP_STR_REG] = &&HANDLER_PVM_A32_OP_STR_REG, + [PVM_A32_OP_STRB_IMM] = &&HANDLER_PVM_A32_OP_STRB_IMM, + [PVM_A32_OP_STRB_REG] = &&HANDLER_PVM_A32_OP_STRB_REG, + [PVM_A32_OP_STRD_IMM] = &&HANDLER_PVM_A32_OP_STRD_IMM, + [PVM_A32_OP_STRD_REG] = &&HANDLER_PVM_A32_OP_STRD_REG, + [PVM_A32_OP_STRH_IMM] = &&HANDLER_PVM_A32_OP_STRH_IMM, + [PVM_A32_OP_STRH_REG] = &&HANDLER_PVM_A32_OP_STRH_REG, + [PVM_A32_OP_LDM] = &&HANDLER_PVM_A32_OP_LDM, + [PVM_A32_OP_LDMDA] = &&HANDLER_PVM_A32_OP_LDMDA, + [PVM_A32_OP_LDMDB] = &&HANDLER_PVM_A32_OP_LDMDB, + [PVM_A32_OP_LDMIB] = &&HANDLER_PVM_A32_OP_LDMIB, + [PVM_A32_OP_LDM_USR] = &&HANDLER_PVM_A32_OP_LDM_USR, + [PVM_A32_OP_LDM_ERET] = &&HANDLER_PVM_A32_OP_LDM_ERET, + [PVM_A32_OP_STM] = &&HANDLER_PVM_A32_OP_STM, + [PVM_A32_OP_STMDA] = &&HANDLER_PVM_A32_OP_STMDA, + [PVM_A32_OP_STMDB] = &&HANDLER_PVM_A32_OP_STMDB, + [PVM_A32_OP_STMIB] = &&HANDLER_PVM_A32_OP_STMIB, + [PVM_A32_OP_STM_USR] = &&HANDLER_PVM_A32_OP_STM_USR, + [PVM_A32_OP_BFC] = &&HANDLER_PVM_A32_OP_BFC, + [PVM_A32_OP_BFI] = &&HANDLER_PVM_A32_OP_BFI, + [PVM_A32_OP_CLZ] = &&HANDLER_PVM_A32_OP_CLZ, + [PVM_A32_OP_MOVT] = &&HANDLER_PVM_A32_OP_MOVT, + [PVM_A32_OP_MOVW] = &&HANDLER_PVM_A32_OP_MOVW, + [PVM_A32_OP_SBFX] = &&HANDLER_PVM_A32_OP_SBFX, + [PVM_A32_OP_SEL] = &&HANDLER_PVM_A32_OP_SEL, + [PVM_A32_OP_UBFX] = &&HANDLER_PVM_A32_OP_UBFX, + [PVM_A32_OP_USAD8] = &&HANDLER_PVM_A32_OP_USAD8, + [PVM_A32_OP_USADA8] = &&HANDLER_PVM_A32_OP_USADA8, + [PVM_A32_OP_PKHBT] = &&HANDLER_PVM_A32_OP_PKHBT, + [PVM_A32_OP_PKHTB] = &&HANDLER_PVM_A32_OP_PKHTB, + [PVM_A32_OP_RBIT] = &&HANDLER_PVM_A32_OP_RBIT, + [PVM_A32_OP_REV] = &&HANDLER_PVM_A32_OP_REV, + [PVM_A32_OP_REV16] = &&HANDLER_PVM_A32_OP_REV16, + [PVM_A32_OP_REVSH] = &&HANDLER_PVM_A32_OP_REVSH, + [PVM_A32_OP_SSAT] = &&HANDLER_PVM_A32_OP_SSAT, + [PVM_A32_OP_SSAT16] = &&HANDLER_PVM_A32_OP_SSAT16, + [PVM_A32_OP_USAT] = &&HANDLER_PVM_A32_OP_USAT, + [PVM_A32_OP_USAT16] = &&HANDLER_PVM_A32_OP_USAT16, + [PVM_A32_OP_SDIV] = &&HANDLER_PVM_A32_OP_SDIV, + [PVM_A32_OP_UDIV] = &&HANDLER_PVM_A32_OP_UDIV, + [PVM_A32_OP_MLA] = &&HANDLER_PVM_A32_OP_MLA, + [PVM_A32_OP_MLS] = &&HANDLER_PVM_A32_OP_MLS, + [PVM_A32_OP_MUL] = &&HANDLER_PVM_A32_OP_MUL, + [PVM_A32_OP_SMLAL] = &&HANDLER_PVM_A32_OP_SMLAL, + [PVM_A32_OP_SMULL] = &&HANDLER_PVM_A32_OP_SMULL, + [PVM_A32_OP_UMAAL] = &&HANDLER_PVM_A32_OP_UMAAL, + [PVM_A32_OP_UMLAL] = &&HANDLER_PVM_A32_OP_UMLAL, + [PVM_A32_OP_UMULL] = &&HANDLER_PVM_A32_OP_UMULL, + [PVM_A32_OP_SMLALXY] = &&HANDLER_PVM_A32_OP_SMLALXY, + [PVM_A32_OP_SMLAXY] = &&HANDLER_PVM_A32_OP_SMLAXY, + [PVM_A32_OP_SMULXY] = &&HANDLER_PVM_A32_OP_SMULXY, + [PVM_A32_OP_SMLAWY] = &&HANDLER_PVM_A32_OP_SMLAWY, + [PVM_A32_OP_SMULWY] = &&HANDLER_PVM_A32_OP_SMULWY, + [PVM_A32_OP_SMMUL] = &&HANDLER_PVM_A32_OP_SMMUL, + [PVM_A32_OP_SMMLA] = &&HANDLER_PVM_A32_OP_SMMLA, + [PVM_A32_OP_SMMLS] = &&HANDLER_PVM_A32_OP_SMMLS, + [PVM_A32_OP_SMUAD] = &&HANDLER_PVM_A32_OP_SMUAD, + [PVM_A32_OP_SMLAD] = &&HANDLER_PVM_A32_OP_SMLAD, + [PVM_A32_OP_SMLALD] = &&HANDLER_PVM_A32_OP_SMLALD, + [PVM_A32_OP_SMUSD] = &&HANDLER_PVM_A32_OP_SMUSD, + [PVM_A32_OP_SMLSD] = &&HANDLER_PVM_A32_OP_SMLSD, + [PVM_A32_OP_SMLSLD] = &&HANDLER_PVM_A32_OP_SMLSLD, + [PVM_A32_OP_SADD8] = &&HANDLER_PVM_A32_OP_SADD8, + [PVM_A32_OP_SADD16] = &&HANDLER_PVM_A32_OP_SADD16, + [PVM_A32_OP_SASX] = &&HANDLER_PVM_A32_OP_SASX, + [PVM_A32_OP_SSAX] = &&HANDLER_PVM_A32_OP_SSAX, + [PVM_A32_OP_SSUB8] = &&HANDLER_PVM_A32_OP_SSUB8, + [PVM_A32_OP_SSUB16] = &&HANDLER_PVM_A32_OP_SSUB16, + [PVM_A32_OP_UADD8] = &&HANDLER_PVM_A32_OP_UADD8, + [PVM_A32_OP_UADD16] = &&HANDLER_PVM_A32_OP_UADD16, + [PVM_A32_OP_UASX] = &&HANDLER_PVM_A32_OP_UASX, + [PVM_A32_OP_USAX] = &&HANDLER_PVM_A32_OP_USAX, + [PVM_A32_OP_USUB8] = &&HANDLER_PVM_A32_OP_USUB8, + [PVM_A32_OP_USUB16] = &&HANDLER_PVM_A32_OP_USUB16, + [PVM_A32_OP_QADD8] = &&HANDLER_PVM_A32_OP_QADD8, + [PVM_A32_OP_QADD16] = &&HANDLER_PVM_A32_OP_QADD16, + [PVM_A32_OP_QASX] = &&HANDLER_PVM_A32_OP_QASX, + [PVM_A32_OP_QSAX] = &&HANDLER_PVM_A32_OP_QSAX, + [PVM_A32_OP_QSUB8] = &&HANDLER_PVM_A32_OP_QSUB8, + [PVM_A32_OP_QSUB16] = &&HANDLER_PVM_A32_OP_QSUB16, + [PVM_A32_OP_UQADD8] = &&HANDLER_PVM_A32_OP_UQADD8, + [PVM_A32_OP_UQADD16] = &&HANDLER_PVM_A32_OP_UQADD16, + [PVM_A32_OP_UQASX] = &&HANDLER_PVM_A32_OP_UQASX, + [PVM_A32_OP_UQSAX] = &&HANDLER_PVM_A32_OP_UQSAX, + [PVM_A32_OP_UQSUB8] = &&HANDLER_PVM_A32_OP_UQSUB8, + [PVM_A32_OP_UQSUB16] = &&HANDLER_PVM_A32_OP_UQSUB16, + [PVM_A32_OP_SHADD8] = &&HANDLER_PVM_A32_OP_SHADD8, + [PVM_A32_OP_SHADD16] = &&HANDLER_PVM_A32_OP_SHADD16, + [PVM_A32_OP_SHASX] = &&HANDLER_PVM_A32_OP_SHASX, + [PVM_A32_OP_SHSAX] = &&HANDLER_PVM_A32_OP_SHSAX, + [PVM_A32_OP_SHSUB8] = &&HANDLER_PVM_A32_OP_SHSUB8, + [PVM_A32_OP_SHSUB16] = &&HANDLER_PVM_A32_OP_SHSUB16, + [PVM_A32_OP_UHADD8] = &&HANDLER_PVM_A32_OP_UHADD8, + [PVM_A32_OP_UHADD16] = &&HANDLER_PVM_A32_OP_UHADD16, + [PVM_A32_OP_UHASX] = &&HANDLER_PVM_A32_OP_UHASX, + [PVM_A32_OP_UHSAX] = &&HANDLER_PVM_A32_OP_UHSAX, + [PVM_A32_OP_UHSUB8] = &&HANDLER_PVM_A32_OP_UHSUB8, + [PVM_A32_OP_UHSUB16] = &&HANDLER_PVM_A32_OP_UHSUB16, + [PVM_A32_OP_QADD] = &&HANDLER_PVM_A32_OP_QADD, + [PVM_A32_OP_QSUB] = &&HANDLER_PVM_A32_OP_QSUB, + [PVM_A32_OP_QDADD] = &&HANDLER_PVM_A32_OP_QDADD, + [PVM_A32_OP_QDSUB] = &&HANDLER_PVM_A32_OP_QDSUB, + [PVM_A32_OP_MRS] = &&HANDLER_PVM_A32_OP_MRS, + [PVM_A32_OP_MSR_IMM] = &&HANDLER_PVM_A32_OP_MSR_IMM, + [PVM_A32_OP_MSR_REG] = &&HANDLER_PVM_A32_OP_MSR_REG, diff --git a/src/jit/interpreter/arm32/handlers.inc b/src/jit/interpreter/arm32/handlers.inc new file mode 100644 index 0000000..06742d7 --- /dev/null +++ b/src/jit/interpreter/arm32/handlers.inc @@ -0,0 +1,1255 @@ +HANDLER(PVM_A32_OP_DMB): { + // TODO: Implement handler for DMB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_DSB): { + // TODO: Implement handler for DSB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ISB): { + // TODO: Implement handler for ISB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BLX_IMM): { + // TODO: Implement handler for BLX (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BLX_REG): { + // TODO: Implement handler for BLX (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_B): { + // TODO: Implement handler for B + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BL): { + // TODO: Implement handler for BL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BX): { + // TODO: Implement handler for BX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BXJ): { + // TODO: Implement handler for BXJ + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RFE): { + // TODO: Implement handler for RFE + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SRS): { + // TODO: Implement handler for SRS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CPS): { + // TODO: Implement handler for CPS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SETEND): { + // TODO: Implement handler for SETEND + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CRC32): { + // TODO: Implement handler for CRC32 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CRC32C): { + // TODO: Implement handler for CRC32C + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CDP): { + // TODO: Implement handler for CDP + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MCR): { + // TODO: Implement handler for MCR + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MCRR): { + // TODO: Implement handler for MCRR + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MRC): { + // TODO: Implement handler for MRC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MRRC): { + // TODO: Implement handler for MRRC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDC): { + // TODO: Implement handler for LDC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STC): { + // TODO: Implement handler for STC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADC_IMM): { + // TODO: Implement handler for ADC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADC_REG): { + // TODO: Implement handler for ADC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADC_RSR): { + // TODO: Implement handler for ADC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADD_IMM): { + // TODO: Implement handler for ADD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADD_REG): { + // TODO: Implement handler for ADD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADD_RSR): { + // TODO: Implement handler for ADD (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_AND_IMM): { + // TODO: Implement handler for AND (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_AND_REG): { + // TODO: Implement handler for AND (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_AND_RSR): { + // TODO: Implement handler for AND (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BIC_IMM): { + // TODO: Implement handler for BIC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BIC_REG): { + // TODO: Implement handler for BIC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BIC_RSR): { + // TODO: Implement handler for BIC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMN_IMM): { + // TODO: Implement handler for CMN (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMN_REG): { + // TODO: Implement handler for CMN (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMN_RSR): { + // TODO: Implement handler for CMN (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMP_IMM): { + // TODO: Implement handler for CMP (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMP_REG): { + // TODO: Implement handler for CMP (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMP_RSR): { + // TODO: Implement handler for CMP (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_EOR_IMM): { + // TODO: Implement handler for EOR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_EOR_REG): { + // TODO: Implement handler for EOR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_EOR_RSR): { + // TODO: Implement handler for EOR (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOV_IMM): { + // TODO: Implement handler for MOV (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOV_REG): { + // TODO: Implement handler for MOV (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOV_RSR): { + // TODO: Implement handler for MOV (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MVN_IMM): { + // TODO: Implement handler for MVN (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MVN_REG): { + // TODO: Implement handler for MVN (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MVN_RSR): { + // TODO: Implement handler for MVN (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ORR_IMM): { + // TODO: Implement handler for ORR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ORR_REG): { + // TODO: Implement handler for ORR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ORR_RSR): { + // TODO: Implement handler for ORR (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSB_IMM): { + // TODO: Implement handler for RSB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSB_REG): { + // TODO: Implement handler for RSB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSB_RSR): { + // TODO: Implement handler for RSB (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSC_IMM): { + // TODO: Implement handler for RSC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSC_REG): { + // TODO: Implement handler for RSC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSC_RSR): { + // TODO: Implement handler for RSC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBC_IMM): { + // TODO: Implement handler for SBC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBC_REG): { + // TODO: Implement handler for SBC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBC_RSR): { + // TODO: Implement handler for SBC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SUB_IMM): { + // TODO: Implement handler for SUB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SUB_REG): { + // TODO: Implement handler for SUB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SUB_RSR): { + // TODO: Implement handler for SUB (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TEQ_IMM): { + // TODO: Implement handler for TEQ (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TEQ_REG): { + // TODO: Implement handler for TEQ (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TEQ_RSR): { + // TODO: Implement handler for TEQ (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TST_IMM): { + // TODO: Implement handler for TST (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TST_REG): { + // TODO: Implement handler for TST (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TST_RSR): { + // TODO: Implement handler for TST (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BKPT): { + // TODO: Implement handler for BKPT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SVC): { + // TODO: Implement handler for SVC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UDF): { + // TODO: Implement handler for UDF + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTB): { + // TODO: Implement handler for SXTB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTB16): { + // TODO: Implement handler for SXTB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTH): { + // TODO: Implement handler for SXTH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTAB): { + // TODO: Implement handler for SXTAB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTAB16): { + // TODO: Implement handler for SXTAB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTAH): { + // TODO: Implement handler for SXTAH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTB): { + // TODO: Implement handler for UXTB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTB16): { + // TODO: Implement handler for UXTB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTH): { + // TODO: Implement handler for UXTH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTAB): { + // TODO: Implement handler for UXTAB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTAB16): { + // TODO: Implement handler for UXTAB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTAH): { + // TODO: Implement handler for UXTAH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PLD_IMM): { + // TODO: Implement handler for PLD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PLD_REG): { + // TODO: Implement handler for PLD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SEV): { + // TODO: Implement handler for SEV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SEVL): { + // TODO: Implement handler for SEVL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_WFE): { + // TODO: Implement handler for WFE + DISPATCH(); +} + +HANDLER(PVM_A32_OP_WFI): { + // TODO: Implement handler for WFI + DISPATCH(); +} + +HANDLER(PVM_A32_OP_YIELD): { + // TODO: Implement handler for YIELD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_NOP): { + // TODO: Implement handler for NOP + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CLREX): { + // TODO: Implement handler for CLREX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SWP): { + // TODO: Implement handler for SWP + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SWPB): { + // TODO: Implement handler for SWPB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STL): { + // TODO: Implement handler for STL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEX): { + // TODO: Implement handler for STLEX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREX): { + // TODO: Implement handler for STREX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDA): { + // TODO: Implement handler for LDA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEX): { + // TODO: Implement handler for LDAEX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREX): { + // TODO: Implement handler for LDREX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEXD): { + // TODO: Implement handler for STLEXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREXD): { + // TODO: Implement handler for STREXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEXD): { + // TODO: Implement handler for LDAEXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREXD): { + // TODO: Implement handler for LDREXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLB): { + // TODO: Implement handler for STLB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEXB): { + // TODO: Implement handler for STLEXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREXB): { + // TODO: Implement handler for STREXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAB): { + // TODO: Implement handler for LDAB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEXB): { + // TODO: Implement handler for LDAEXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREXB): { + // TODO: Implement handler for LDREXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLH): { + // TODO: Implement handler for STLH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEXH): { + // TODO: Implement handler for STLEXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREXH): { + // TODO: Implement handler for STREXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAH): { + // TODO: Implement handler for LDAH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEXH): { + // TODO: Implement handler for LDAEXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREXH): { + // TODO: Implement handler for LDREXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRBT): { + // TODO: Implement handler for LDRBT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRHT): { + // TODO: Implement handler for LDRHT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSBT): { + // TODO: Implement handler for LDRSBT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSHT): { + // TODO: Implement handler for LDRSHT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRT): { + // TODO: Implement handler for LDRT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRBT): { + // TODO: Implement handler for STRBT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRHT): { + // TODO: Implement handler for STRHT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRT): { + // TODO: Implement handler for STRT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDR_LIT): { + // TODO: Implement handler for LDR (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDR_IMM): { + // TODO: Implement handler for LDR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDR_REG): { + // TODO: Implement handler for LDR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRB_LIT): { + // TODO: Implement handler for LDRB (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRB_IMM): { + // TODO: Implement handler for LDRB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRB_REG): { + // TODO: Implement handler for LDRB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRD_LIT): { + // TODO: Implement handler for LDRD (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRD_IMM): { + // TODO: Implement handler for LDRD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRD_REG): { + // TODO: Implement handler for LDRD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRH_LIT): { + // TODO: Implement handler for LDRH (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRH_IMM): { + // TODO: Implement handler for LDRH (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRH_REG): { + // TODO: Implement handler for LDRH (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSB_LIT): { + // TODO: Implement handler for LDRSB (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSB_IMM): { + // TODO: Implement handler for LDRSB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSB_REG): { + // TODO: Implement handler for LDRSB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSH_LIT): { + // TODO: Implement handler for LDRSH (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSH_IMM): { + // TODO: Implement handler for LDRSH (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSH_REG): { + // TODO: Implement handler for LDRSH (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STR_IMM): { + // TODO: Implement handler for STR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STR_REG): { + // TODO: Implement handler for STR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRB_IMM): { + // TODO: Implement handler for STRB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRB_REG): { + // TODO: Implement handler for STRB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRD_IMM): { + // TODO: Implement handler for STRD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRD_REG): { + // TODO: Implement handler for STRD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRH_IMM): { + // TODO: Implement handler for STRH (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRH_REG): { + // TODO: Implement handler for STRH (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDM): { + // TODO: Implement handler for LDM + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDMDA): { + // TODO: Implement handler for LDMDA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDMDB): { + // TODO: Implement handler for LDMDB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDMIB): { + // TODO: Implement handler for LDMIB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDM_USR): { + // TODO: Implement handler for LDM (usr reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDM_ERET): { + // TODO: Implement handler for LDM (exce ret) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STM): { + // TODO: Implement handler for STM + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STMDA): { + // TODO: Implement handler for STMDA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STMDB): { + // TODO: Implement handler for STMDB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STMIB): { + // TODO: Implement handler for STMIB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STM_USR): { + // TODO: Implement handler for STM (usr reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BFC): { + // TODO: Implement handler for BFC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BFI): { + // TODO: Implement handler for BFI + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CLZ): { + // TODO: Implement handler for CLZ + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOVT): { + // TODO: Implement handler for MOVT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOVW): { + // TODO: Implement handler for MOVW + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBFX): { + // TODO: Implement handler for SBFX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SEL): { + // TODO: Implement handler for SEL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UBFX): { + // TODO: Implement handler for UBFX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAD8): { + // TODO: Implement handler for USAD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USADA8): { + // TODO: Implement handler for USADA8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PKHBT): { + // TODO: Implement handler for PKHBT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PKHTB): { + // TODO: Implement handler for PKHTB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RBIT): { + // TODO: Implement handler for RBIT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_REV): { + // TODO: Implement handler for REV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_REV16): { + // TODO: Implement handler for REV16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_REVSH): { + // TODO: Implement handler for REVSH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSAT): { + // TODO: Implement handler for SSAT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSAT16): { + // TODO: Implement handler for SSAT16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAT): { + // TODO: Implement handler for USAT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAT16): { + // TODO: Implement handler for USAT16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SDIV): { + // TODO: Implement handler for SDIV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UDIV): { + // TODO: Implement handler for UDIV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MLA): { + // TODO: Implement handler for MLA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MLS): { + // TODO: Implement handler for MLS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MUL): { + // TODO: Implement handler for MUL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAL): { + // TODO: Implement handler for SMLAL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMULL): { + // TODO: Implement handler for SMULL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UMAAL): { + // TODO: Implement handler for UMAAL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UMLAL): { + // TODO: Implement handler for UMLAL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UMULL): { + // TODO: Implement handler for UMULL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLALXY): { + // TODO: Implement handler for SMLALXY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAXY): { + // TODO: Implement handler for SMLAXY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMULXY): { + // TODO: Implement handler for SMULXY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAWY): { + // TODO: Implement handler for SMLAWY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMULWY): { + // TODO: Implement handler for SMULWY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMMUL): { + // TODO: Implement handler for SMMUL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMMLA): { + // TODO: Implement handler for SMMLA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMMLS): { + // TODO: Implement handler for SMMLS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMUAD): { + // TODO: Implement handler for SMUAD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAD): { + // TODO: Implement handler for SMLAD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLALD): { + // TODO: Implement handler for SMLALD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMUSD): { + // TODO: Implement handler for SMUSD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLSD): { + // TODO: Implement handler for SMLSD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLSLD): { + // TODO: Implement handler for SMLSLD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SADD8): { + // TODO: Implement handler for SADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SADD16): { + // TODO: Implement handler for SADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SASX): { + // TODO: Implement handler for SASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSAX): { + // TODO: Implement handler for SSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSUB8): { + // TODO: Implement handler for SSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSUB16): { + // TODO: Implement handler for SSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UADD8): { + // TODO: Implement handler for UADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UADD16): { + // TODO: Implement handler for UADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UASX): { + // TODO: Implement handler for UASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAX): { + // TODO: Implement handler for USAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USUB8): { + // TODO: Implement handler for USUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USUB16): { + // TODO: Implement handler for USUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QADD8): { + // TODO: Implement handler for QADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QADD16): { + // TODO: Implement handler for QADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QASX): { + // TODO: Implement handler for QASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSAX): { + // TODO: Implement handler for QSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSUB8): { + // TODO: Implement handler for QSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSUB16): { + // TODO: Implement handler for QSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQADD8): { + // TODO: Implement handler for UQADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQADD16): { + // TODO: Implement handler for UQADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQASX): { + // TODO: Implement handler for UQASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQSAX): { + // TODO: Implement handler for UQSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQSUB8): { + // TODO: Implement handler for UQSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQSUB16): { + // TODO: Implement handler for UQSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHADD8): { + // TODO: Implement handler for SHADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHADD16): { + // TODO: Implement handler for SHADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHASX): { + // TODO: Implement handler for SHASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHSAX): { + // TODO: Implement handler for SHSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHSUB8): { + // TODO: Implement handler for SHSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHSUB16): { + // TODO: Implement handler for SHSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHADD8): { + // TODO: Implement handler for UHADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHADD16): { + // TODO: Implement handler for UHADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHASX): { + // TODO: Implement handler for UHASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHSAX): { + // TODO: Implement handler for UHSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHSUB8): { + // TODO: Implement handler for UHSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHSUB16): { + // TODO: Implement handler for UHSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QADD): { + // TODO: Implement handler for QADD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSUB): { + // TODO: Implement handler for QSUB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QDADD): { + // TODO: Implement handler for QDADD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QDSUB): { + // TODO: Implement handler for QDSUB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MRS): { + // TODO: Implement handler for MRS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MSR_IMM): { + // TODO: Implement handler for MSR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MSR_REG): { + // TODO: Implement handler for MSR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STOP): { + // TODO: Implement handler for PVM_A32_OP_STOP + DISPATCH(); +} + diff --git a/src/jit/interpreter/arm32/handlers.inc.skeleton b/src/jit/interpreter/arm32/handlers.inc.skeleton new file mode 100644 index 0000000..d237da0 --- /dev/null +++ b/src/jit/interpreter/arm32/handlers.inc.skeleton @@ -0,0 +1,1261 @@ +/* + * GENERATED FILE - DO NOT EDIT + * This file is generated by scripts/generate_jit_assets.py + * This file contains pre-generated, empty handler blocks for the every instruction. + */ + +HANDLER(PVM_A32_OP_DMB): { + // TODO: Implement handler for DMB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_DSB): { + // TODO: Implement handler for DSB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ISB): { + // TODO: Implement handler for ISB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BLX_IMM): { + // TODO: Implement handler for BLX (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BLX_REG): { + // TODO: Implement handler for BLX (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_B): { + // TODO: Implement handler for B + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BL): { + // TODO: Implement handler for BL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BX): { + // TODO: Implement handler for BX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BXJ): { + // TODO: Implement handler for BXJ + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RFE): { + // TODO: Implement handler for RFE + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SRS): { + // TODO: Implement handler for SRS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CPS): { + // TODO: Implement handler for CPS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SETEND): { + // TODO: Implement handler for SETEND + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CRC32): { + // TODO: Implement handler for CRC32 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CRC32C): { + // TODO: Implement handler for CRC32C + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CDP): { + // TODO: Implement handler for CDP + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MCR): { + // TODO: Implement handler for MCR + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MCRR): { + // TODO: Implement handler for MCRR + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MRC): { + // TODO: Implement handler for MRC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MRRC): { + // TODO: Implement handler for MRRC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDC): { + // TODO: Implement handler for LDC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STC): { + // TODO: Implement handler for STC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADC_IMM): { + // TODO: Implement handler for ADC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADC_REG): { + // TODO: Implement handler for ADC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADC_RSR): { + // TODO: Implement handler for ADC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADD_IMM): { + // TODO: Implement handler for ADD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADD_REG): { + // TODO: Implement handler for ADD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ADD_RSR): { + // TODO: Implement handler for ADD (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_AND_IMM): { + // TODO: Implement handler for AND (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_AND_REG): { + // TODO: Implement handler for AND (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_AND_RSR): { + // TODO: Implement handler for AND (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BIC_IMM): { + // TODO: Implement handler for BIC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BIC_REG): { + // TODO: Implement handler for BIC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BIC_RSR): { + // TODO: Implement handler for BIC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMN_IMM): { + // TODO: Implement handler for CMN (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMN_REG): { + // TODO: Implement handler for CMN (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMN_RSR): { + // TODO: Implement handler for CMN (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMP_IMM): { + // TODO: Implement handler for CMP (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMP_REG): { + // TODO: Implement handler for CMP (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CMP_RSR): { + // TODO: Implement handler for CMP (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_EOR_IMM): { + // TODO: Implement handler for EOR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_EOR_REG): { + // TODO: Implement handler for EOR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_EOR_RSR): { + // TODO: Implement handler for EOR (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOV_IMM): { + // TODO: Implement handler for MOV (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOV_REG): { + // TODO: Implement handler for MOV (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOV_RSR): { + // TODO: Implement handler for MOV (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MVN_IMM): { + // TODO: Implement handler for MVN (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MVN_REG): { + // TODO: Implement handler for MVN (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MVN_RSR): { + // TODO: Implement handler for MVN (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ORR_IMM): { + // TODO: Implement handler for ORR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ORR_REG): { + // TODO: Implement handler for ORR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_ORR_RSR): { + // TODO: Implement handler for ORR (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSB_IMM): { + // TODO: Implement handler for RSB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSB_REG): { + // TODO: Implement handler for RSB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSB_RSR): { + // TODO: Implement handler for RSB (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSC_IMM): { + // TODO: Implement handler for RSC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSC_REG): { + // TODO: Implement handler for RSC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RSC_RSR): { + // TODO: Implement handler for RSC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBC_IMM): { + // TODO: Implement handler for SBC (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBC_REG): { + // TODO: Implement handler for SBC (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBC_RSR): { + // TODO: Implement handler for SBC (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SUB_IMM): { + // TODO: Implement handler for SUB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SUB_REG): { + // TODO: Implement handler for SUB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SUB_RSR): { + // TODO: Implement handler for SUB (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TEQ_IMM): { + // TODO: Implement handler for TEQ (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TEQ_REG): { + // TODO: Implement handler for TEQ (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TEQ_RSR): { + // TODO: Implement handler for TEQ (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TST_IMM): { + // TODO: Implement handler for TST (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TST_REG): { + // TODO: Implement handler for TST (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_TST_RSR): { + // TODO: Implement handler for TST (rsr) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BKPT): { + // TODO: Implement handler for BKPT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SVC): { + // TODO: Implement handler for SVC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UDF): { + // TODO: Implement handler for UDF + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTB): { + // TODO: Implement handler for SXTB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTB16): { + // TODO: Implement handler for SXTB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTH): { + // TODO: Implement handler for SXTH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTAB): { + // TODO: Implement handler for SXTAB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTAB16): { + // TODO: Implement handler for SXTAB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SXTAH): { + // TODO: Implement handler for SXTAH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTB): { + // TODO: Implement handler for UXTB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTB16): { + // TODO: Implement handler for UXTB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTH): { + // TODO: Implement handler for UXTH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTAB): { + // TODO: Implement handler for UXTAB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTAB16): { + // TODO: Implement handler for UXTAB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UXTAH): { + // TODO: Implement handler for UXTAH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PLD_IMM): { + // TODO: Implement handler for PLD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PLD_REG): { + // TODO: Implement handler for PLD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SEV): { + // TODO: Implement handler for SEV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SEVL): { + // TODO: Implement handler for SEVL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_WFE): { + // TODO: Implement handler for WFE + DISPATCH(); +} + +HANDLER(PVM_A32_OP_WFI): { + // TODO: Implement handler for WFI + DISPATCH(); +} + +HANDLER(PVM_A32_OP_YIELD): { + // TODO: Implement handler for YIELD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_NOP): { + // TODO: Implement handler for NOP + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CLREX): { + // TODO: Implement handler for CLREX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SWP): { + // TODO: Implement handler for SWP + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SWPB): { + // TODO: Implement handler for SWPB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STL): { + // TODO: Implement handler for STL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEX): { + // TODO: Implement handler for STLEX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREX): { + // TODO: Implement handler for STREX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDA): { + // TODO: Implement handler for LDA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEX): { + // TODO: Implement handler for LDAEX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREX): { + // TODO: Implement handler for LDREX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEXD): { + // TODO: Implement handler for STLEXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREXD): { + // TODO: Implement handler for STREXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEXD): { + // TODO: Implement handler for LDAEXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREXD): { + // TODO: Implement handler for LDREXD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLB): { + // TODO: Implement handler for STLB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEXB): { + // TODO: Implement handler for STLEXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREXB): { + // TODO: Implement handler for STREXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAB): { + // TODO: Implement handler for LDAB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEXB): { + // TODO: Implement handler for LDAEXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREXB): { + // TODO: Implement handler for LDREXB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLH): { + // TODO: Implement handler for STLH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STLEXH): { + // TODO: Implement handler for STLEXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STREXH): { + // TODO: Implement handler for STREXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAH): { + // TODO: Implement handler for LDAH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDAEXH): { + // TODO: Implement handler for LDAEXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDREXH): { + // TODO: Implement handler for LDREXH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRBT): { + // TODO: Implement handler for LDRBT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRHT): { + // TODO: Implement handler for LDRHT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSBT): { + // TODO: Implement handler for LDRSBT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSHT): { + // TODO: Implement handler for LDRSHT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRT): { + // TODO: Implement handler for LDRT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRBT): { + // TODO: Implement handler for STRBT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRHT): { + // TODO: Implement handler for STRHT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRT): { + // TODO: Implement handler for STRT (A1) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDR_LIT): { + // TODO: Implement handler for LDR (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDR_IMM): { + // TODO: Implement handler for LDR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDR_REG): { + // TODO: Implement handler for LDR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRB_LIT): { + // TODO: Implement handler for LDRB (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRB_IMM): { + // TODO: Implement handler for LDRB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRB_REG): { + // TODO: Implement handler for LDRB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRD_LIT): { + // TODO: Implement handler for LDRD (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRD_IMM): { + // TODO: Implement handler for LDRD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRD_REG): { + // TODO: Implement handler for LDRD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRH_LIT): { + // TODO: Implement handler for LDRH (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRH_IMM): { + // TODO: Implement handler for LDRH (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRH_REG): { + // TODO: Implement handler for LDRH (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSB_LIT): { + // TODO: Implement handler for LDRSB (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSB_IMM): { + // TODO: Implement handler for LDRSB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSB_REG): { + // TODO: Implement handler for LDRSB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSH_LIT): { + // TODO: Implement handler for LDRSH (lit) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSH_IMM): { + // TODO: Implement handler for LDRSH (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDRSH_REG): { + // TODO: Implement handler for LDRSH (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STR_IMM): { + // TODO: Implement handler for STR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STR_REG): { + // TODO: Implement handler for STR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRB_IMM): { + // TODO: Implement handler for STRB (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRB_REG): { + // TODO: Implement handler for STRB (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRD_IMM): { + // TODO: Implement handler for STRD (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRD_REG): { + // TODO: Implement handler for STRD (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRH_IMM): { + // TODO: Implement handler for STRH (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STRH_REG): { + // TODO: Implement handler for STRH (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDM): { + // TODO: Implement handler for LDM + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDMDA): { + // TODO: Implement handler for LDMDA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDMDB): { + // TODO: Implement handler for LDMDB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDMIB): { + // TODO: Implement handler for LDMIB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDM_USR): { + // TODO: Implement handler for LDM (usr reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_LDM_ERET): { + // TODO: Implement handler for LDM (exce ret) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STM): { + // TODO: Implement handler for STM + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STMDA): { + // TODO: Implement handler for STMDA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STMDB): { + // TODO: Implement handler for STMDB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STMIB): { + // TODO: Implement handler for STMIB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STM_USR): { + // TODO: Implement handler for STM (usr reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BFC): { + // TODO: Implement handler for BFC + DISPATCH(); +} + +HANDLER(PVM_A32_OP_BFI): { + // TODO: Implement handler for BFI + DISPATCH(); +} + +HANDLER(PVM_A32_OP_CLZ): { + // TODO: Implement handler for CLZ + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOVT): { + // TODO: Implement handler for MOVT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MOVW): { + // TODO: Implement handler for MOVW + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SBFX): { + // TODO: Implement handler for SBFX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SEL): { + // TODO: Implement handler for SEL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UBFX): { + // TODO: Implement handler for UBFX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAD8): { + // TODO: Implement handler for USAD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USADA8): { + // TODO: Implement handler for USADA8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PKHBT): { + // TODO: Implement handler for PKHBT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_PKHTB): { + // TODO: Implement handler for PKHTB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_RBIT): { + // TODO: Implement handler for RBIT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_REV): { + // TODO: Implement handler for REV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_REV16): { + // TODO: Implement handler for REV16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_REVSH): { + // TODO: Implement handler for REVSH + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSAT): { + // TODO: Implement handler for SSAT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSAT16): { + // TODO: Implement handler for SSAT16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAT): { + // TODO: Implement handler for USAT + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAT16): { + // TODO: Implement handler for USAT16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SDIV): { + // TODO: Implement handler for SDIV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UDIV): { + // TODO: Implement handler for UDIV + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MLA): { + // TODO: Implement handler for MLA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MLS): { + // TODO: Implement handler for MLS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MUL): { + // TODO: Implement handler for MUL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAL): { + // TODO: Implement handler for SMLAL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMULL): { + // TODO: Implement handler for SMULL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UMAAL): { + // TODO: Implement handler for UMAAL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UMLAL): { + // TODO: Implement handler for UMLAL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UMULL): { + // TODO: Implement handler for UMULL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLALXY): { + // TODO: Implement handler for SMLALXY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAXY): { + // TODO: Implement handler for SMLAXY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMULXY): { + // TODO: Implement handler for SMULXY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAWY): { + // TODO: Implement handler for SMLAWY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMULWY): { + // TODO: Implement handler for SMULWY + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMMUL): { + // TODO: Implement handler for SMMUL + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMMLA): { + // TODO: Implement handler for SMMLA + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMMLS): { + // TODO: Implement handler for SMMLS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMUAD): { + // TODO: Implement handler for SMUAD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLAD): { + // TODO: Implement handler for SMLAD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLALD): { + // TODO: Implement handler for SMLALD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMUSD): { + // TODO: Implement handler for SMUSD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLSD): { + // TODO: Implement handler for SMLSD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SMLSLD): { + // TODO: Implement handler for SMLSLD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SADD8): { + // TODO: Implement handler for SADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SADD16): { + // TODO: Implement handler for SADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SASX): { + // TODO: Implement handler for SASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSAX): { + // TODO: Implement handler for SSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSUB8): { + // TODO: Implement handler for SSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SSUB16): { + // TODO: Implement handler for SSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UADD8): { + // TODO: Implement handler for UADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UADD16): { + // TODO: Implement handler for UADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UASX): { + // TODO: Implement handler for UASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USAX): { + // TODO: Implement handler for USAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USUB8): { + // TODO: Implement handler for USUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_USUB16): { + // TODO: Implement handler for USUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QADD8): { + // TODO: Implement handler for QADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QADD16): { + // TODO: Implement handler for QADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QASX): { + // TODO: Implement handler for QASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSAX): { + // TODO: Implement handler for QSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSUB8): { + // TODO: Implement handler for QSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSUB16): { + // TODO: Implement handler for QSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQADD8): { + // TODO: Implement handler for UQADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQADD16): { + // TODO: Implement handler for UQADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQASX): { + // TODO: Implement handler for UQASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQSAX): { + // TODO: Implement handler for UQSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQSUB8): { + // TODO: Implement handler for UQSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UQSUB16): { + // TODO: Implement handler for UQSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHADD8): { + // TODO: Implement handler for SHADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHADD16): { + // TODO: Implement handler for SHADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHASX): { + // TODO: Implement handler for SHASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHSAX): { + // TODO: Implement handler for SHSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHSUB8): { + // TODO: Implement handler for SHSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_SHSUB16): { + // TODO: Implement handler for SHSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHADD8): { + // TODO: Implement handler for UHADD8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHADD16): { + // TODO: Implement handler for UHADD16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHASX): { + // TODO: Implement handler for UHASX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHSAX): { + // TODO: Implement handler for UHSAX + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHSUB8): { + // TODO: Implement handler for UHSUB8 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_UHSUB16): { + // TODO: Implement handler for UHSUB16 + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QADD): { + // TODO: Implement handler for QADD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QSUB): { + // TODO: Implement handler for QSUB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QDADD): { + // TODO: Implement handler for QDADD + DISPATCH(); +} + +HANDLER(PVM_A32_OP_QDSUB): { + // TODO: Implement handler for QDSUB + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MRS): { + // TODO: Implement handler for MRS + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MSR_IMM): { + // TODO: Implement handler for MSR (imm) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_MSR_REG): { + // TODO: Implement handler for MSR (reg) + DISPATCH(); +} + +HANDLER(PVM_A32_OP_STOP): { + // TODO: Implement handler for PVM_A32_OP_STOP + DISPATCH(); +} + diff --git a/src/jit/interpreter/arm32/instruction.c b/src/jit/interpreter/arm32/instruction.c new file mode 100644 index 0000000..f2a7a32 --- /dev/null +++ b/src/jit/interpreter/arm32/instruction.c @@ -0,0 +1,47 @@ +/* + * THIS FILE IS A WORK IN PROGRESS AND WILL BE RE-WRITTEN + * Defines pvm_jit_interpreter_instruction_t struct and its internal opcodes. + */ + +#include "frontend/decoder/arm32_opcodes.h" +#include +#if defined(__GNUC__) || defined(__clang__) + #define HANDLER(name) HANDLER_##name + #define DISPATCH() do { \ + instr++; \ + goto *dispatch_table[instr->opcode]; \ + } while(0) +#else + #define HANDLER(name) case name + #define DISPATCH() goto dispatch_loop +#endif + +typedef struct +{ + pvm_jit_decoder_arm32_opcode_t opcode; +} instruction_t; + +void +temp(void) +{ + instruction_t *instr = malloc(sizeof(*instr)); + instr->opcode = PVM_A32_OP_STOP; +#if defined(__GNUC__) || defined(__clang__) + static const void* const dispatch_table[] = { + #include "handler_table.inc" + }; + + // Initial dispatch + goto *dispatch_table[instr->opcode]; +#else + dispatch_loop: + switch (instr->opcode) { +#endif + + #include "handlers.inc" + +#if !defined(__GNUC__) && !defined(__clang__) + default: goto HANDLER_PVM_A32_OP_STOP; + } +#endif +} diff --git a/src/jit/interpreter/a32/translator.c b/src/jit/interpreter/arm32/translator.c similarity index 100% rename from src/jit/interpreter/a32/translator.c rename to src/jit/interpreter/arm32/translator.c From 0d957968dfd50d785af504b5ec3f9520216fce4e Mon Sep 17 00:00:00 2001 From: Ronald Caesar Date: Sat, 6 Dec 2025 01:47:38 -0400 Subject: [PATCH 3/3] jit/interpreter: Organize ifdefs Signed-off-by: Ronald Caesar --- scripts/generate_jit_assets.py | 5 +- src/jit/interpreter/arm32/handler_table.inc | 503 ++++++++++---------- src/jit/interpreter/arm32/handlers.inc | 4 +- src/jit/interpreter/arm32/instruction.c | 100 +++- src/jit/interpreter/arm32/instruction.h | 1 + 5 files changed, 333 insertions(+), 280 deletions(-) create mode 100644 src/jit/interpreter/arm32/instruction.h diff --git a/scripts/generate_jit_assets.py b/scripts/generate_jit_assets.py index a8b158b..0c4bbb5 100644 --- a/scripts/generate_jit_assets.py +++ b/scripts/generate_jit_assets.py @@ -179,13 +179,12 @@ def write_interpreter_handler_table(path, instructions): print(f"Generating interpreter handler table: {path}") seen = set() with open(path, "w") as f: - f.write("/* GENERATED FILE - DO NOT EDIT */\n") - f.write("/* This file is generated by scripts/generate_jit_assets.py */\n") for inst in instructions: enum_name = f"PVM_A32_OP_{inst.name.upper()}" if enum_name not in seen: - f.write(f" [{enum_name}] = &&HANDLER_{enum_name},\n") + f.write(f" [{enum_name}] = &&{enum_name},\n") seen.add(enum_name) + f.write(f" [PVM_A32_OP_STOP] = &&PVM_A32_OP_STOP,\n") def write_interpreter_handler_skeletons(path, instructions): diff --git a/src/jit/interpreter/arm32/handler_table.inc b/src/jit/interpreter/arm32/handler_table.inc index 6c6b528..3342edd 100644 --- a/src/jit/interpreter/arm32/handler_table.inc +++ b/src/jit/interpreter/arm32/handler_table.inc @@ -1,252 +1,251 @@ -/* GENERATED FILE - DO NOT EDIT */ -/* This file is generated by scripts/generate_jit_assets.py */ - [PVM_A32_OP_DMB] = &&HANDLER_PVM_A32_OP_DMB, - [PVM_A32_OP_DSB] = &&HANDLER_PVM_A32_OP_DSB, - [PVM_A32_OP_ISB] = &&HANDLER_PVM_A32_OP_ISB, - [PVM_A32_OP_BLX_IMM] = &&HANDLER_PVM_A32_OP_BLX_IMM, - [PVM_A32_OP_BLX_REG] = &&HANDLER_PVM_A32_OP_BLX_REG, - [PVM_A32_OP_B] = &&HANDLER_PVM_A32_OP_B, - [PVM_A32_OP_BL] = &&HANDLER_PVM_A32_OP_BL, - [PVM_A32_OP_BX] = &&HANDLER_PVM_A32_OP_BX, - [PVM_A32_OP_BXJ] = &&HANDLER_PVM_A32_OP_BXJ, - [PVM_A32_OP_RFE] = &&HANDLER_PVM_A32_OP_RFE, - [PVM_A32_OP_SRS] = &&HANDLER_PVM_A32_OP_SRS, - [PVM_A32_OP_CPS] = &&HANDLER_PVM_A32_OP_CPS, - [PVM_A32_OP_SETEND] = &&HANDLER_PVM_A32_OP_SETEND, - [PVM_A32_OP_CRC32] = &&HANDLER_PVM_A32_OP_CRC32, - [PVM_A32_OP_CRC32C] = &&HANDLER_PVM_A32_OP_CRC32C, - [PVM_A32_OP_CDP] = &&HANDLER_PVM_A32_OP_CDP, - [PVM_A32_OP_MCR] = &&HANDLER_PVM_A32_OP_MCR, - [PVM_A32_OP_MCRR] = &&HANDLER_PVM_A32_OP_MCRR, - [PVM_A32_OP_MRC] = &&HANDLER_PVM_A32_OP_MRC, - [PVM_A32_OP_MRRC] = &&HANDLER_PVM_A32_OP_MRRC, - [PVM_A32_OP_LDC] = &&HANDLER_PVM_A32_OP_LDC, - [PVM_A32_OP_STC] = &&HANDLER_PVM_A32_OP_STC, - [PVM_A32_OP_ADC_IMM] = &&HANDLER_PVM_A32_OP_ADC_IMM, - [PVM_A32_OP_ADC_REG] = &&HANDLER_PVM_A32_OP_ADC_REG, - [PVM_A32_OP_ADC_RSR] = &&HANDLER_PVM_A32_OP_ADC_RSR, - [PVM_A32_OP_ADD_IMM] = &&HANDLER_PVM_A32_OP_ADD_IMM, - [PVM_A32_OP_ADD_REG] = &&HANDLER_PVM_A32_OP_ADD_REG, - [PVM_A32_OP_ADD_RSR] = &&HANDLER_PVM_A32_OP_ADD_RSR, - [PVM_A32_OP_AND_IMM] = &&HANDLER_PVM_A32_OP_AND_IMM, - [PVM_A32_OP_AND_REG] = &&HANDLER_PVM_A32_OP_AND_REG, - [PVM_A32_OP_AND_RSR] = &&HANDLER_PVM_A32_OP_AND_RSR, - [PVM_A32_OP_BIC_IMM] = &&HANDLER_PVM_A32_OP_BIC_IMM, - [PVM_A32_OP_BIC_REG] = &&HANDLER_PVM_A32_OP_BIC_REG, - [PVM_A32_OP_BIC_RSR] = &&HANDLER_PVM_A32_OP_BIC_RSR, - [PVM_A32_OP_CMN_IMM] = &&HANDLER_PVM_A32_OP_CMN_IMM, - [PVM_A32_OP_CMN_REG] = &&HANDLER_PVM_A32_OP_CMN_REG, - [PVM_A32_OP_CMN_RSR] = &&HANDLER_PVM_A32_OP_CMN_RSR, - [PVM_A32_OP_CMP_IMM] = &&HANDLER_PVM_A32_OP_CMP_IMM, - [PVM_A32_OP_CMP_REG] = &&HANDLER_PVM_A32_OP_CMP_REG, - [PVM_A32_OP_CMP_RSR] = &&HANDLER_PVM_A32_OP_CMP_RSR, - [PVM_A32_OP_EOR_IMM] = &&HANDLER_PVM_A32_OP_EOR_IMM, - [PVM_A32_OP_EOR_REG] = &&HANDLER_PVM_A32_OP_EOR_REG, - [PVM_A32_OP_EOR_RSR] = &&HANDLER_PVM_A32_OP_EOR_RSR, - [PVM_A32_OP_MOV_IMM] = &&HANDLER_PVM_A32_OP_MOV_IMM, - [PVM_A32_OP_MOV_REG] = &&HANDLER_PVM_A32_OP_MOV_REG, - [PVM_A32_OP_MOV_RSR] = &&HANDLER_PVM_A32_OP_MOV_RSR, - [PVM_A32_OP_MVN_IMM] = &&HANDLER_PVM_A32_OP_MVN_IMM, - [PVM_A32_OP_MVN_REG] = &&HANDLER_PVM_A32_OP_MVN_REG, - [PVM_A32_OP_MVN_RSR] = &&HANDLER_PVM_A32_OP_MVN_RSR, - [PVM_A32_OP_ORR_IMM] = &&HANDLER_PVM_A32_OP_ORR_IMM, - [PVM_A32_OP_ORR_REG] = &&HANDLER_PVM_A32_OP_ORR_REG, - [PVM_A32_OP_ORR_RSR] = &&HANDLER_PVM_A32_OP_ORR_RSR, - [PVM_A32_OP_RSB_IMM] = &&HANDLER_PVM_A32_OP_RSB_IMM, - [PVM_A32_OP_RSB_REG] = &&HANDLER_PVM_A32_OP_RSB_REG, - [PVM_A32_OP_RSB_RSR] = &&HANDLER_PVM_A32_OP_RSB_RSR, - [PVM_A32_OP_RSC_IMM] = &&HANDLER_PVM_A32_OP_RSC_IMM, - [PVM_A32_OP_RSC_REG] = &&HANDLER_PVM_A32_OP_RSC_REG, - [PVM_A32_OP_RSC_RSR] = &&HANDLER_PVM_A32_OP_RSC_RSR, - [PVM_A32_OP_SBC_IMM] = &&HANDLER_PVM_A32_OP_SBC_IMM, - [PVM_A32_OP_SBC_REG] = &&HANDLER_PVM_A32_OP_SBC_REG, - [PVM_A32_OP_SBC_RSR] = &&HANDLER_PVM_A32_OP_SBC_RSR, - [PVM_A32_OP_SUB_IMM] = &&HANDLER_PVM_A32_OP_SUB_IMM, - [PVM_A32_OP_SUB_REG] = &&HANDLER_PVM_A32_OP_SUB_REG, - [PVM_A32_OP_SUB_RSR] = &&HANDLER_PVM_A32_OP_SUB_RSR, - [PVM_A32_OP_TEQ_IMM] = &&HANDLER_PVM_A32_OP_TEQ_IMM, - [PVM_A32_OP_TEQ_REG] = &&HANDLER_PVM_A32_OP_TEQ_REG, - [PVM_A32_OP_TEQ_RSR] = &&HANDLER_PVM_A32_OP_TEQ_RSR, - [PVM_A32_OP_TST_IMM] = &&HANDLER_PVM_A32_OP_TST_IMM, - [PVM_A32_OP_TST_REG] = &&HANDLER_PVM_A32_OP_TST_REG, - [PVM_A32_OP_TST_RSR] = &&HANDLER_PVM_A32_OP_TST_RSR, - [PVM_A32_OP_BKPT] = &&HANDLER_PVM_A32_OP_BKPT, - [PVM_A32_OP_SVC] = &&HANDLER_PVM_A32_OP_SVC, - [PVM_A32_OP_UDF] = &&HANDLER_PVM_A32_OP_UDF, - [PVM_A32_OP_SXTB] = &&HANDLER_PVM_A32_OP_SXTB, - [PVM_A32_OP_SXTB16] = &&HANDLER_PVM_A32_OP_SXTB16, - [PVM_A32_OP_SXTH] = &&HANDLER_PVM_A32_OP_SXTH, - [PVM_A32_OP_SXTAB] = &&HANDLER_PVM_A32_OP_SXTAB, - [PVM_A32_OP_SXTAB16] = &&HANDLER_PVM_A32_OP_SXTAB16, - [PVM_A32_OP_SXTAH] = &&HANDLER_PVM_A32_OP_SXTAH, - [PVM_A32_OP_UXTB] = &&HANDLER_PVM_A32_OP_UXTB, - [PVM_A32_OP_UXTB16] = &&HANDLER_PVM_A32_OP_UXTB16, - [PVM_A32_OP_UXTH] = &&HANDLER_PVM_A32_OP_UXTH, - [PVM_A32_OP_UXTAB] = &&HANDLER_PVM_A32_OP_UXTAB, - [PVM_A32_OP_UXTAB16] = &&HANDLER_PVM_A32_OP_UXTAB16, - [PVM_A32_OP_UXTAH] = &&HANDLER_PVM_A32_OP_UXTAH, - [PVM_A32_OP_PLD_IMM] = &&HANDLER_PVM_A32_OP_PLD_IMM, - [PVM_A32_OP_PLD_REG] = &&HANDLER_PVM_A32_OP_PLD_REG, - [PVM_A32_OP_SEV] = &&HANDLER_PVM_A32_OP_SEV, - [PVM_A32_OP_SEVL] = &&HANDLER_PVM_A32_OP_SEVL, - [PVM_A32_OP_WFE] = &&HANDLER_PVM_A32_OP_WFE, - [PVM_A32_OP_WFI] = &&HANDLER_PVM_A32_OP_WFI, - [PVM_A32_OP_YIELD] = &&HANDLER_PVM_A32_OP_YIELD, - [PVM_A32_OP_NOP] = &&HANDLER_PVM_A32_OP_NOP, - [PVM_A32_OP_CLREX] = &&HANDLER_PVM_A32_OP_CLREX, - [PVM_A32_OP_SWP] = &&HANDLER_PVM_A32_OP_SWP, - [PVM_A32_OP_SWPB] = &&HANDLER_PVM_A32_OP_SWPB, - [PVM_A32_OP_STL] = &&HANDLER_PVM_A32_OP_STL, - [PVM_A32_OP_STLEX] = &&HANDLER_PVM_A32_OP_STLEX, - [PVM_A32_OP_STREX] = &&HANDLER_PVM_A32_OP_STREX, - [PVM_A32_OP_LDA] = &&HANDLER_PVM_A32_OP_LDA, - [PVM_A32_OP_LDAEX] = &&HANDLER_PVM_A32_OP_LDAEX, - [PVM_A32_OP_LDREX] = &&HANDLER_PVM_A32_OP_LDREX, - [PVM_A32_OP_STLEXD] = &&HANDLER_PVM_A32_OP_STLEXD, - [PVM_A32_OP_STREXD] = &&HANDLER_PVM_A32_OP_STREXD, - [PVM_A32_OP_LDAEXD] = &&HANDLER_PVM_A32_OP_LDAEXD, - [PVM_A32_OP_LDREXD] = &&HANDLER_PVM_A32_OP_LDREXD, - [PVM_A32_OP_STLB] = &&HANDLER_PVM_A32_OP_STLB, - [PVM_A32_OP_STLEXB] = &&HANDLER_PVM_A32_OP_STLEXB, - [PVM_A32_OP_STREXB] = &&HANDLER_PVM_A32_OP_STREXB, - [PVM_A32_OP_LDAB] = &&HANDLER_PVM_A32_OP_LDAB, - [PVM_A32_OP_LDAEXB] = &&HANDLER_PVM_A32_OP_LDAEXB, - [PVM_A32_OP_LDREXB] = &&HANDLER_PVM_A32_OP_LDREXB, - [PVM_A32_OP_STLH] = &&HANDLER_PVM_A32_OP_STLH, - [PVM_A32_OP_STLEXH] = &&HANDLER_PVM_A32_OP_STLEXH, - [PVM_A32_OP_STREXH] = &&HANDLER_PVM_A32_OP_STREXH, - [PVM_A32_OP_LDAH] = &&HANDLER_PVM_A32_OP_LDAH, - [PVM_A32_OP_LDAEXH] = &&HANDLER_PVM_A32_OP_LDAEXH, - [PVM_A32_OP_LDREXH] = &&HANDLER_PVM_A32_OP_LDREXH, - [PVM_A32_OP_LDRBT] = &&HANDLER_PVM_A32_OP_LDRBT, - [PVM_A32_OP_LDRHT] = &&HANDLER_PVM_A32_OP_LDRHT, - [PVM_A32_OP_LDRSBT] = &&HANDLER_PVM_A32_OP_LDRSBT, - [PVM_A32_OP_LDRSHT] = &&HANDLER_PVM_A32_OP_LDRSHT, - [PVM_A32_OP_LDRT] = &&HANDLER_PVM_A32_OP_LDRT, - [PVM_A32_OP_STRBT] = &&HANDLER_PVM_A32_OP_STRBT, - [PVM_A32_OP_STRHT] = &&HANDLER_PVM_A32_OP_STRHT, - [PVM_A32_OP_STRT] = &&HANDLER_PVM_A32_OP_STRT, - [PVM_A32_OP_LDR_LIT] = &&HANDLER_PVM_A32_OP_LDR_LIT, - [PVM_A32_OP_LDR_IMM] = &&HANDLER_PVM_A32_OP_LDR_IMM, - [PVM_A32_OP_LDR_REG] = &&HANDLER_PVM_A32_OP_LDR_REG, - [PVM_A32_OP_LDRB_LIT] = &&HANDLER_PVM_A32_OP_LDRB_LIT, - [PVM_A32_OP_LDRB_IMM] = &&HANDLER_PVM_A32_OP_LDRB_IMM, - [PVM_A32_OP_LDRB_REG] = &&HANDLER_PVM_A32_OP_LDRB_REG, - [PVM_A32_OP_LDRD_LIT] = &&HANDLER_PVM_A32_OP_LDRD_LIT, - [PVM_A32_OP_LDRD_IMM] = &&HANDLER_PVM_A32_OP_LDRD_IMM, - [PVM_A32_OP_LDRD_REG] = &&HANDLER_PVM_A32_OP_LDRD_REG, - [PVM_A32_OP_LDRH_LIT] = &&HANDLER_PVM_A32_OP_LDRH_LIT, - [PVM_A32_OP_LDRH_IMM] = &&HANDLER_PVM_A32_OP_LDRH_IMM, - [PVM_A32_OP_LDRH_REG] = &&HANDLER_PVM_A32_OP_LDRH_REG, - [PVM_A32_OP_LDRSB_LIT] = &&HANDLER_PVM_A32_OP_LDRSB_LIT, - [PVM_A32_OP_LDRSB_IMM] = &&HANDLER_PVM_A32_OP_LDRSB_IMM, - [PVM_A32_OP_LDRSB_REG] = &&HANDLER_PVM_A32_OP_LDRSB_REG, - [PVM_A32_OP_LDRSH_LIT] = &&HANDLER_PVM_A32_OP_LDRSH_LIT, - [PVM_A32_OP_LDRSH_IMM] = &&HANDLER_PVM_A32_OP_LDRSH_IMM, - [PVM_A32_OP_LDRSH_REG] = &&HANDLER_PVM_A32_OP_LDRSH_REG, - [PVM_A32_OP_STR_IMM] = &&HANDLER_PVM_A32_OP_STR_IMM, - [PVM_A32_OP_STR_REG] = &&HANDLER_PVM_A32_OP_STR_REG, - [PVM_A32_OP_STRB_IMM] = &&HANDLER_PVM_A32_OP_STRB_IMM, - [PVM_A32_OP_STRB_REG] = &&HANDLER_PVM_A32_OP_STRB_REG, - [PVM_A32_OP_STRD_IMM] = &&HANDLER_PVM_A32_OP_STRD_IMM, - [PVM_A32_OP_STRD_REG] = &&HANDLER_PVM_A32_OP_STRD_REG, - [PVM_A32_OP_STRH_IMM] = &&HANDLER_PVM_A32_OP_STRH_IMM, - [PVM_A32_OP_STRH_REG] = &&HANDLER_PVM_A32_OP_STRH_REG, - [PVM_A32_OP_LDM] = &&HANDLER_PVM_A32_OP_LDM, - [PVM_A32_OP_LDMDA] = &&HANDLER_PVM_A32_OP_LDMDA, - [PVM_A32_OP_LDMDB] = &&HANDLER_PVM_A32_OP_LDMDB, - [PVM_A32_OP_LDMIB] = &&HANDLER_PVM_A32_OP_LDMIB, - [PVM_A32_OP_LDM_USR] = &&HANDLER_PVM_A32_OP_LDM_USR, - [PVM_A32_OP_LDM_ERET] = &&HANDLER_PVM_A32_OP_LDM_ERET, - [PVM_A32_OP_STM] = &&HANDLER_PVM_A32_OP_STM, - [PVM_A32_OP_STMDA] = &&HANDLER_PVM_A32_OP_STMDA, - [PVM_A32_OP_STMDB] = &&HANDLER_PVM_A32_OP_STMDB, - [PVM_A32_OP_STMIB] = &&HANDLER_PVM_A32_OP_STMIB, - [PVM_A32_OP_STM_USR] = &&HANDLER_PVM_A32_OP_STM_USR, - [PVM_A32_OP_BFC] = &&HANDLER_PVM_A32_OP_BFC, - [PVM_A32_OP_BFI] = &&HANDLER_PVM_A32_OP_BFI, - [PVM_A32_OP_CLZ] = &&HANDLER_PVM_A32_OP_CLZ, - [PVM_A32_OP_MOVT] = &&HANDLER_PVM_A32_OP_MOVT, - [PVM_A32_OP_MOVW] = &&HANDLER_PVM_A32_OP_MOVW, - [PVM_A32_OP_SBFX] = &&HANDLER_PVM_A32_OP_SBFX, - [PVM_A32_OP_SEL] = &&HANDLER_PVM_A32_OP_SEL, - [PVM_A32_OP_UBFX] = &&HANDLER_PVM_A32_OP_UBFX, - [PVM_A32_OP_USAD8] = &&HANDLER_PVM_A32_OP_USAD8, - [PVM_A32_OP_USADA8] = &&HANDLER_PVM_A32_OP_USADA8, - [PVM_A32_OP_PKHBT] = &&HANDLER_PVM_A32_OP_PKHBT, - [PVM_A32_OP_PKHTB] = &&HANDLER_PVM_A32_OP_PKHTB, - [PVM_A32_OP_RBIT] = &&HANDLER_PVM_A32_OP_RBIT, - [PVM_A32_OP_REV] = &&HANDLER_PVM_A32_OP_REV, - [PVM_A32_OP_REV16] = &&HANDLER_PVM_A32_OP_REV16, - [PVM_A32_OP_REVSH] = &&HANDLER_PVM_A32_OP_REVSH, - [PVM_A32_OP_SSAT] = &&HANDLER_PVM_A32_OP_SSAT, - [PVM_A32_OP_SSAT16] = &&HANDLER_PVM_A32_OP_SSAT16, - [PVM_A32_OP_USAT] = &&HANDLER_PVM_A32_OP_USAT, - [PVM_A32_OP_USAT16] = &&HANDLER_PVM_A32_OP_USAT16, - [PVM_A32_OP_SDIV] = &&HANDLER_PVM_A32_OP_SDIV, - [PVM_A32_OP_UDIV] = &&HANDLER_PVM_A32_OP_UDIV, - [PVM_A32_OP_MLA] = &&HANDLER_PVM_A32_OP_MLA, - [PVM_A32_OP_MLS] = &&HANDLER_PVM_A32_OP_MLS, - [PVM_A32_OP_MUL] = &&HANDLER_PVM_A32_OP_MUL, - [PVM_A32_OP_SMLAL] = &&HANDLER_PVM_A32_OP_SMLAL, - [PVM_A32_OP_SMULL] = &&HANDLER_PVM_A32_OP_SMULL, - [PVM_A32_OP_UMAAL] = &&HANDLER_PVM_A32_OP_UMAAL, - [PVM_A32_OP_UMLAL] = &&HANDLER_PVM_A32_OP_UMLAL, - [PVM_A32_OP_UMULL] = &&HANDLER_PVM_A32_OP_UMULL, - [PVM_A32_OP_SMLALXY] = &&HANDLER_PVM_A32_OP_SMLALXY, - [PVM_A32_OP_SMLAXY] = &&HANDLER_PVM_A32_OP_SMLAXY, - [PVM_A32_OP_SMULXY] = &&HANDLER_PVM_A32_OP_SMULXY, - [PVM_A32_OP_SMLAWY] = &&HANDLER_PVM_A32_OP_SMLAWY, - [PVM_A32_OP_SMULWY] = &&HANDLER_PVM_A32_OP_SMULWY, - [PVM_A32_OP_SMMUL] = &&HANDLER_PVM_A32_OP_SMMUL, - [PVM_A32_OP_SMMLA] = &&HANDLER_PVM_A32_OP_SMMLA, - [PVM_A32_OP_SMMLS] = &&HANDLER_PVM_A32_OP_SMMLS, - [PVM_A32_OP_SMUAD] = &&HANDLER_PVM_A32_OP_SMUAD, - [PVM_A32_OP_SMLAD] = &&HANDLER_PVM_A32_OP_SMLAD, - [PVM_A32_OP_SMLALD] = &&HANDLER_PVM_A32_OP_SMLALD, - [PVM_A32_OP_SMUSD] = &&HANDLER_PVM_A32_OP_SMUSD, - [PVM_A32_OP_SMLSD] = &&HANDLER_PVM_A32_OP_SMLSD, - [PVM_A32_OP_SMLSLD] = &&HANDLER_PVM_A32_OP_SMLSLD, - [PVM_A32_OP_SADD8] = &&HANDLER_PVM_A32_OP_SADD8, - [PVM_A32_OP_SADD16] = &&HANDLER_PVM_A32_OP_SADD16, - [PVM_A32_OP_SASX] = &&HANDLER_PVM_A32_OP_SASX, - [PVM_A32_OP_SSAX] = &&HANDLER_PVM_A32_OP_SSAX, - [PVM_A32_OP_SSUB8] = &&HANDLER_PVM_A32_OP_SSUB8, - [PVM_A32_OP_SSUB16] = &&HANDLER_PVM_A32_OP_SSUB16, - [PVM_A32_OP_UADD8] = &&HANDLER_PVM_A32_OP_UADD8, - [PVM_A32_OP_UADD16] = &&HANDLER_PVM_A32_OP_UADD16, - [PVM_A32_OP_UASX] = &&HANDLER_PVM_A32_OP_UASX, - [PVM_A32_OP_USAX] = &&HANDLER_PVM_A32_OP_USAX, - [PVM_A32_OP_USUB8] = &&HANDLER_PVM_A32_OP_USUB8, - [PVM_A32_OP_USUB16] = &&HANDLER_PVM_A32_OP_USUB16, - [PVM_A32_OP_QADD8] = &&HANDLER_PVM_A32_OP_QADD8, - [PVM_A32_OP_QADD16] = &&HANDLER_PVM_A32_OP_QADD16, - [PVM_A32_OP_QASX] = &&HANDLER_PVM_A32_OP_QASX, - [PVM_A32_OP_QSAX] = &&HANDLER_PVM_A32_OP_QSAX, - [PVM_A32_OP_QSUB8] = &&HANDLER_PVM_A32_OP_QSUB8, - [PVM_A32_OP_QSUB16] = &&HANDLER_PVM_A32_OP_QSUB16, - [PVM_A32_OP_UQADD8] = &&HANDLER_PVM_A32_OP_UQADD8, - [PVM_A32_OP_UQADD16] = &&HANDLER_PVM_A32_OP_UQADD16, - [PVM_A32_OP_UQASX] = &&HANDLER_PVM_A32_OP_UQASX, - [PVM_A32_OP_UQSAX] = &&HANDLER_PVM_A32_OP_UQSAX, - [PVM_A32_OP_UQSUB8] = &&HANDLER_PVM_A32_OP_UQSUB8, - [PVM_A32_OP_UQSUB16] = &&HANDLER_PVM_A32_OP_UQSUB16, - [PVM_A32_OP_SHADD8] = &&HANDLER_PVM_A32_OP_SHADD8, - [PVM_A32_OP_SHADD16] = &&HANDLER_PVM_A32_OP_SHADD16, - [PVM_A32_OP_SHASX] = &&HANDLER_PVM_A32_OP_SHASX, - [PVM_A32_OP_SHSAX] = &&HANDLER_PVM_A32_OP_SHSAX, - [PVM_A32_OP_SHSUB8] = &&HANDLER_PVM_A32_OP_SHSUB8, - [PVM_A32_OP_SHSUB16] = &&HANDLER_PVM_A32_OP_SHSUB16, - [PVM_A32_OP_UHADD8] = &&HANDLER_PVM_A32_OP_UHADD8, - [PVM_A32_OP_UHADD16] = &&HANDLER_PVM_A32_OP_UHADD16, - [PVM_A32_OP_UHASX] = &&HANDLER_PVM_A32_OP_UHASX, - [PVM_A32_OP_UHSAX] = &&HANDLER_PVM_A32_OP_UHSAX, - [PVM_A32_OP_UHSUB8] = &&HANDLER_PVM_A32_OP_UHSUB8, - [PVM_A32_OP_UHSUB16] = &&HANDLER_PVM_A32_OP_UHSUB16, - [PVM_A32_OP_QADD] = &&HANDLER_PVM_A32_OP_QADD, - [PVM_A32_OP_QSUB] = &&HANDLER_PVM_A32_OP_QSUB, - [PVM_A32_OP_QDADD] = &&HANDLER_PVM_A32_OP_QDADD, - [PVM_A32_OP_QDSUB] = &&HANDLER_PVM_A32_OP_QDSUB, - [PVM_A32_OP_MRS] = &&HANDLER_PVM_A32_OP_MRS, - [PVM_A32_OP_MSR_IMM] = &&HANDLER_PVM_A32_OP_MSR_IMM, - [PVM_A32_OP_MSR_REG] = &&HANDLER_PVM_A32_OP_MSR_REG, + [PVM_A32_OP_DMB] = &&PVM_A32_OP_DMB, + [PVM_A32_OP_DSB] = &&PVM_A32_OP_DSB, + [PVM_A32_OP_ISB] = &&PVM_A32_OP_ISB, + [PVM_A32_OP_BLX_IMM] = &&PVM_A32_OP_BLX_IMM, + [PVM_A32_OP_BLX_REG] = &&PVM_A32_OP_BLX_REG, + [PVM_A32_OP_B] = &&PVM_A32_OP_B, + [PVM_A32_OP_BL] = &&PVM_A32_OP_BL, + [PVM_A32_OP_BX] = &&PVM_A32_OP_BX, + [PVM_A32_OP_BXJ] = &&PVM_A32_OP_BXJ, + [PVM_A32_OP_RFE] = &&PVM_A32_OP_RFE, + [PVM_A32_OP_SRS] = &&PVM_A32_OP_SRS, + [PVM_A32_OP_CPS] = &&PVM_A32_OP_CPS, + [PVM_A32_OP_SETEND] = &&PVM_A32_OP_SETEND, + [PVM_A32_OP_CRC32] = &&PVM_A32_OP_CRC32, + [PVM_A32_OP_CRC32C] = &&PVM_A32_OP_CRC32C, + [PVM_A32_OP_CDP] = &&PVM_A32_OP_CDP, + [PVM_A32_OP_MCR] = &&PVM_A32_OP_MCR, + [PVM_A32_OP_MCRR] = &&PVM_A32_OP_MCRR, + [PVM_A32_OP_MRC] = &&PVM_A32_OP_MRC, + [PVM_A32_OP_MRRC] = &&PVM_A32_OP_MRRC, + [PVM_A32_OP_LDC] = &&PVM_A32_OP_LDC, + [PVM_A32_OP_STC] = &&PVM_A32_OP_STC, + [PVM_A32_OP_ADC_IMM] = &&PVM_A32_OP_ADC_IMM, + [PVM_A32_OP_ADC_REG] = &&PVM_A32_OP_ADC_REG, + [PVM_A32_OP_ADC_RSR] = &&PVM_A32_OP_ADC_RSR, + [PVM_A32_OP_ADD_IMM] = &&PVM_A32_OP_ADD_IMM, + [PVM_A32_OP_ADD_REG] = &&PVM_A32_OP_ADD_REG, + [PVM_A32_OP_ADD_RSR] = &&PVM_A32_OP_ADD_RSR, + [PVM_A32_OP_AND_IMM] = &&PVM_A32_OP_AND_IMM, + [PVM_A32_OP_AND_REG] = &&PVM_A32_OP_AND_REG, + [PVM_A32_OP_AND_RSR] = &&PVM_A32_OP_AND_RSR, + [PVM_A32_OP_BIC_IMM] = &&PVM_A32_OP_BIC_IMM, + [PVM_A32_OP_BIC_REG] = &&PVM_A32_OP_BIC_REG, + [PVM_A32_OP_BIC_RSR] = &&PVM_A32_OP_BIC_RSR, + [PVM_A32_OP_CMN_IMM] = &&PVM_A32_OP_CMN_IMM, + [PVM_A32_OP_CMN_REG] = &&PVM_A32_OP_CMN_REG, + [PVM_A32_OP_CMN_RSR] = &&PVM_A32_OP_CMN_RSR, + [PVM_A32_OP_CMP_IMM] = &&PVM_A32_OP_CMP_IMM, + [PVM_A32_OP_CMP_REG] = &&PVM_A32_OP_CMP_REG, + [PVM_A32_OP_CMP_RSR] = &&PVM_A32_OP_CMP_RSR, + [PVM_A32_OP_EOR_IMM] = &&PVM_A32_OP_EOR_IMM, + [PVM_A32_OP_EOR_REG] = &&PVM_A32_OP_EOR_REG, + [PVM_A32_OP_EOR_RSR] = &&PVM_A32_OP_EOR_RSR, + [PVM_A32_OP_MOV_IMM] = &&PVM_A32_OP_MOV_IMM, + [PVM_A32_OP_MOV_REG] = &&PVM_A32_OP_MOV_REG, + [PVM_A32_OP_MOV_RSR] = &&PVM_A32_OP_MOV_RSR, + [PVM_A32_OP_MVN_IMM] = &&PVM_A32_OP_MVN_IMM, + [PVM_A32_OP_MVN_REG] = &&PVM_A32_OP_MVN_REG, + [PVM_A32_OP_MVN_RSR] = &&PVM_A32_OP_MVN_RSR, + [PVM_A32_OP_ORR_IMM] = &&PVM_A32_OP_ORR_IMM, + [PVM_A32_OP_ORR_REG] = &&PVM_A32_OP_ORR_REG, + [PVM_A32_OP_ORR_RSR] = &&PVM_A32_OP_ORR_RSR, + [PVM_A32_OP_RSB_IMM] = &&PVM_A32_OP_RSB_IMM, + [PVM_A32_OP_RSB_REG] = &&PVM_A32_OP_RSB_REG, + [PVM_A32_OP_RSB_RSR] = &&PVM_A32_OP_RSB_RSR, + [PVM_A32_OP_RSC_IMM] = &&PVM_A32_OP_RSC_IMM, + [PVM_A32_OP_RSC_REG] = &&PVM_A32_OP_RSC_REG, + [PVM_A32_OP_RSC_RSR] = &&PVM_A32_OP_RSC_RSR, + [PVM_A32_OP_SBC_IMM] = &&PVM_A32_OP_SBC_IMM, + [PVM_A32_OP_SBC_REG] = &&PVM_A32_OP_SBC_REG, + [PVM_A32_OP_SBC_RSR] = &&PVM_A32_OP_SBC_RSR, + [PVM_A32_OP_SUB_IMM] = &&PVM_A32_OP_SUB_IMM, + [PVM_A32_OP_SUB_REG] = &&PVM_A32_OP_SUB_REG, + [PVM_A32_OP_SUB_RSR] = &&PVM_A32_OP_SUB_RSR, + [PVM_A32_OP_TEQ_IMM] = &&PVM_A32_OP_TEQ_IMM, + [PVM_A32_OP_TEQ_REG] = &&PVM_A32_OP_TEQ_REG, + [PVM_A32_OP_TEQ_RSR] = &&PVM_A32_OP_TEQ_RSR, + [PVM_A32_OP_TST_IMM] = &&PVM_A32_OP_TST_IMM, + [PVM_A32_OP_TST_REG] = &&PVM_A32_OP_TST_REG, + [PVM_A32_OP_TST_RSR] = &&PVM_A32_OP_TST_RSR, + [PVM_A32_OP_BKPT] = &&PVM_A32_OP_BKPT, + [PVM_A32_OP_SVC] = &&PVM_A32_OP_SVC, + [PVM_A32_OP_UDF] = &&PVM_A32_OP_UDF, + [PVM_A32_OP_SXTB] = &&PVM_A32_OP_SXTB, + [PVM_A32_OP_SXTB16] = &&PVM_A32_OP_SXTB16, + [PVM_A32_OP_SXTH] = &&PVM_A32_OP_SXTH, + [PVM_A32_OP_SXTAB] = &&PVM_A32_OP_SXTAB, + [PVM_A32_OP_SXTAB16] = &&PVM_A32_OP_SXTAB16, + [PVM_A32_OP_SXTAH] = &&PVM_A32_OP_SXTAH, + [PVM_A32_OP_UXTB] = &&PVM_A32_OP_UXTB, + [PVM_A32_OP_UXTB16] = &&PVM_A32_OP_UXTB16, + [PVM_A32_OP_UXTH] = &&PVM_A32_OP_UXTH, + [PVM_A32_OP_UXTAB] = &&PVM_A32_OP_UXTAB, + [PVM_A32_OP_UXTAB16] = &&PVM_A32_OP_UXTAB16, + [PVM_A32_OP_UXTAH] = &&PVM_A32_OP_UXTAH, + [PVM_A32_OP_PLD_IMM] = &&PVM_A32_OP_PLD_IMM, + [PVM_A32_OP_PLD_REG] = &&PVM_A32_OP_PLD_REG, + [PVM_A32_OP_SEV] = &&PVM_A32_OP_SEV, + [PVM_A32_OP_SEVL] = &&PVM_A32_OP_SEVL, + [PVM_A32_OP_WFE] = &&PVM_A32_OP_WFE, + [PVM_A32_OP_WFI] = &&PVM_A32_OP_WFI, + [PVM_A32_OP_YIELD] = &&PVM_A32_OP_YIELD, + [PVM_A32_OP_NOP] = &&PVM_A32_OP_NOP, + [PVM_A32_OP_CLREX] = &&PVM_A32_OP_CLREX, + [PVM_A32_OP_SWP] = &&PVM_A32_OP_SWP, + [PVM_A32_OP_SWPB] = &&PVM_A32_OP_SWPB, + [PVM_A32_OP_STL] = &&PVM_A32_OP_STL, + [PVM_A32_OP_STLEX] = &&PVM_A32_OP_STLEX, + [PVM_A32_OP_STREX] = &&PVM_A32_OP_STREX, + [PVM_A32_OP_LDA] = &&PVM_A32_OP_LDA, + [PVM_A32_OP_LDAEX] = &&PVM_A32_OP_LDAEX, + [PVM_A32_OP_LDREX] = &&PVM_A32_OP_LDREX, + [PVM_A32_OP_STLEXD] = &&PVM_A32_OP_STLEXD, + [PVM_A32_OP_STREXD] = &&PVM_A32_OP_STREXD, + [PVM_A32_OP_LDAEXD] = &&PVM_A32_OP_LDAEXD, + [PVM_A32_OP_LDREXD] = &&PVM_A32_OP_LDREXD, + [PVM_A32_OP_STLB] = &&PVM_A32_OP_STLB, + [PVM_A32_OP_STLEXB] = &&PVM_A32_OP_STLEXB, + [PVM_A32_OP_STREXB] = &&PVM_A32_OP_STREXB, + [PVM_A32_OP_LDAB] = &&PVM_A32_OP_LDAB, + [PVM_A32_OP_LDAEXB] = &&PVM_A32_OP_LDAEXB, + [PVM_A32_OP_LDREXB] = &&PVM_A32_OP_LDREXB, + [PVM_A32_OP_STLH] = &&PVM_A32_OP_STLH, + [PVM_A32_OP_STLEXH] = &&PVM_A32_OP_STLEXH, + [PVM_A32_OP_STREXH] = &&PVM_A32_OP_STREXH, + [PVM_A32_OP_LDAH] = &&PVM_A32_OP_LDAH, + [PVM_A32_OP_LDAEXH] = &&PVM_A32_OP_LDAEXH, + [PVM_A32_OP_LDREXH] = &&PVM_A32_OP_LDREXH, + [PVM_A32_OP_LDRBT] = &&PVM_A32_OP_LDRBT, + [PVM_A32_OP_LDRHT] = &&PVM_A32_OP_LDRHT, + [PVM_A32_OP_LDRSBT] = &&PVM_A32_OP_LDRSBT, + [PVM_A32_OP_LDRSHT] = &&PVM_A32_OP_LDRSHT, + [PVM_A32_OP_LDRT] = &&PVM_A32_OP_LDRT, + [PVM_A32_OP_STRBT] = &&PVM_A32_OP_STRBT, + [PVM_A32_OP_STRHT] = &&PVM_A32_OP_STRHT, + [PVM_A32_OP_STRT] = &&PVM_A32_OP_STRT, + [PVM_A32_OP_LDR_LIT] = &&PVM_A32_OP_LDR_LIT, + [PVM_A32_OP_LDR_IMM] = &&PVM_A32_OP_LDR_IMM, + [PVM_A32_OP_LDR_REG] = &&PVM_A32_OP_LDR_REG, + [PVM_A32_OP_LDRB_LIT] = &&PVM_A32_OP_LDRB_LIT, + [PVM_A32_OP_LDRB_IMM] = &&PVM_A32_OP_LDRB_IMM, + [PVM_A32_OP_LDRB_REG] = &&PVM_A32_OP_LDRB_REG, + [PVM_A32_OP_LDRD_LIT] = &&PVM_A32_OP_LDRD_LIT, + [PVM_A32_OP_LDRD_IMM] = &&PVM_A32_OP_LDRD_IMM, + [PVM_A32_OP_LDRD_REG] = &&PVM_A32_OP_LDRD_REG, + [PVM_A32_OP_LDRH_LIT] = &&PVM_A32_OP_LDRH_LIT, + [PVM_A32_OP_LDRH_IMM] = &&PVM_A32_OP_LDRH_IMM, + [PVM_A32_OP_LDRH_REG] = &&PVM_A32_OP_LDRH_REG, + [PVM_A32_OP_LDRSB_LIT] = &&PVM_A32_OP_LDRSB_LIT, + [PVM_A32_OP_LDRSB_IMM] = &&PVM_A32_OP_LDRSB_IMM, + [PVM_A32_OP_LDRSB_REG] = &&PVM_A32_OP_LDRSB_REG, + [PVM_A32_OP_LDRSH_LIT] = &&PVM_A32_OP_LDRSH_LIT, + [PVM_A32_OP_LDRSH_IMM] = &&PVM_A32_OP_LDRSH_IMM, + [PVM_A32_OP_LDRSH_REG] = &&PVM_A32_OP_LDRSH_REG, + [PVM_A32_OP_STR_IMM] = &&PVM_A32_OP_STR_IMM, + [PVM_A32_OP_STR_REG] = &&PVM_A32_OP_STR_REG, + [PVM_A32_OP_STRB_IMM] = &&PVM_A32_OP_STRB_IMM, + [PVM_A32_OP_STRB_REG] = &&PVM_A32_OP_STRB_REG, + [PVM_A32_OP_STRD_IMM] = &&PVM_A32_OP_STRD_IMM, + [PVM_A32_OP_STRD_REG] = &&PVM_A32_OP_STRD_REG, + [PVM_A32_OP_STRH_IMM] = &&PVM_A32_OP_STRH_IMM, + [PVM_A32_OP_STRH_REG] = &&PVM_A32_OP_STRH_REG, + [PVM_A32_OP_LDM] = &&PVM_A32_OP_LDM, + [PVM_A32_OP_LDMDA] = &&PVM_A32_OP_LDMDA, + [PVM_A32_OP_LDMDB] = &&PVM_A32_OP_LDMDB, + [PVM_A32_OP_LDMIB] = &&PVM_A32_OP_LDMIB, + [PVM_A32_OP_LDM_USR] = &&PVM_A32_OP_LDM_USR, + [PVM_A32_OP_LDM_ERET] = &&PVM_A32_OP_LDM_ERET, + [PVM_A32_OP_STM] = &&PVM_A32_OP_STM, + [PVM_A32_OP_STMDA] = &&PVM_A32_OP_STMDA, + [PVM_A32_OP_STMDB] = &&PVM_A32_OP_STMDB, + [PVM_A32_OP_STMIB] = &&PVM_A32_OP_STMIB, + [PVM_A32_OP_STM_USR] = &&PVM_A32_OP_STM_USR, + [PVM_A32_OP_BFC] = &&PVM_A32_OP_BFC, + [PVM_A32_OP_BFI] = &&PVM_A32_OP_BFI, + [PVM_A32_OP_CLZ] = &&PVM_A32_OP_CLZ, + [PVM_A32_OP_MOVT] = &&PVM_A32_OP_MOVT, + [PVM_A32_OP_MOVW] = &&PVM_A32_OP_MOVW, + [PVM_A32_OP_SBFX] = &&PVM_A32_OP_SBFX, + [PVM_A32_OP_SEL] = &&PVM_A32_OP_SEL, + [PVM_A32_OP_UBFX] = &&PVM_A32_OP_UBFX, + [PVM_A32_OP_USAD8] = &&PVM_A32_OP_USAD8, + [PVM_A32_OP_USADA8] = &&PVM_A32_OP_USADA8, + [PVM_A32_OP_PKHBT] = &&PVM_A32_OP_PKHBT, + [PVM_A32_OP_PKHTB] = &&PVM_A32_OP_PKHTB, + [PVM_A32_OP_RBIT] = &&PVM_A32_OP_RBIT, + [PVM_A32_OP_REV] = &&PVM_A32_OP_REV, + [PVM_A32_OP_REV16] = &&PVM_A32_OP_REV16, + [PVM_A32_OP_REVSH] = &&PVM_A32_OP_REVSH, + [PVM_A32_OP_SSAT] = &&PVM_A32_OP_SSAT, + [PVM_A32_OP_SSAT16] = &&PVM_A32_OP_SSAT16, + [PVM_A32_OP_USAT] = &&PVM_A32_OP_USAT, + [PVM_A32_OP_USAT16] = &&PVM_A32_OP_USAT16, + [PVM_A32_OP_SDIV] = &&PVM_A32_OP_SDIV, + [PVM_A32_OP_UDIV] = &&PVM_A32_OP_UDIV, + [PVM_A32_OP_MLA] = &&PVM_A32_OP_MLA, + [PVM_A32_OP_MLS] = &&PVM_A32_OP_MLS, + [PVM_A32_OP_MUL] = &&PVM_A32_OP_MUL, + [PVM_A32_OP_SMLAL] = &&PVM_A32_OP_SMLAL, + [PVM_A32_OP_SMULL] = &&PVM_A32_OP_SMULL, + [PVM_A32_OP_UMAAL] = &&PVM_A32_OP_UMAAL, + [PVM_A32_OP_UMLAL] = &&PVM_A32_OP_UMLAL, + [PVM_A32_OP_UMULL] = &&PVM_A32_OP_UMULL, + [PVM_A32_OP_SMLALXY] = &&PVM_A32_OP_SMLALXY, + [PVM_A32_OP_SMLAXY] = &&PVM_A32_OP_SMLAXY, + [PVM_A32_OP_SMULXY] = &&PVM_A32_OP_SMULXY, + [PVM_A32_OP_SMLAWY] = &&PVM_A32_OP_SMLAWY, + [PVM_A32_OP_SMULWY] = &&PVM_A32_OP_SMULWY, + [PVM_A32_OP_SMMUL] = &&PVM_A32_OP_SMMUL, + [PVM_A32_OP_SMMLA] = &&PVM_A32_OP_SMMLA, + [PVM_A32_OP_SMMLS] = &&PVM_A32_OP_SMMLS, + [PVM_A32_OP_SMUAD] = &&PVM_A32_OP_SMUAD, + [PVM_A32_OP_SMLAD] = &&PVM_A32_OP_SMLAD, + [PVM_A32_OP_SMLALD] = &&PVM_A32_OP_SMLALD, + [PVM_A32_OP_SMUSD] = &&PVM_A32_OP_SMUSD, + [PVM_A32_OP_SMLSD] = &&PVM_A32_OP_SMLSD, + [PVM_A32_OP_SMLSLD] = &&PVM_A32_OP_SMLSLD, + [PVM_A32_OP_SADD8] = &&PVM_A32_OP_SADD8, + [PVM_A32_OP_SADD16] = &&PVM_A32_OP_SADD16, + [PVM_A32_OP_SASX] = &&PVM_A32_OP_SASX, + [PVM_A32_OP_SSAX] = &&PVM_A32_OP_SSAX, + [PVM_A32_OP_SSUB8] = &&PVM_A32_OP_SSUB8, + [PVM_A32_OP_SSUB16] = &&PVM_A32_OP_SSUB16, + [PVM_A32_OP_UADD8] = &&PVM_A32_OP_UADD8, + [PVM_A32_OP_UADD16] = &&PVM_A32_OP_UADD16, + [PVM_A32_OP_UASX] = &&PVM_A32_OP_UASX, + [PVM_A32_OP_USAX] = &&PVM_A32_OP_USAX, + [PVM_A32_OP_USUB8] = &&PVM_A32_OP_USUB8, + [PVM_A32_OP_USUB16] = &&PVM_A32_OP_USUB16, + [PVM_A32_OP_QADD8] = &&PVM_A32_OP_QADD8, + [PVM_A32_OP_QADD16] = &&PVM_A32_OP_QADD16, + [PVM_A32_OP_QASX] = &&PVM_A32_OP_QASX, + [PVM_A32_OP_QSAX] = &&PVM_A32_OP_QSAX, + [PVM_A32_OP_QSUB8] = &&PVM_A32_OP_QSUB8, + [PVM_A32_OP_QSUB16] = &&PVM_A32_OP_QSUB16, + [PVM_A32_OP_UQADD8] = &&PVM_A32_OP_UQADD8, + [PVM_A32_OP_UQADD16] = &&PVM_A32_OP_UQADD16, + [PVM_A32_OP_UQASX] = &&PVM_A32_OP_UQASX, + [PVM_A32_OP_UQSAX] = &&PVM_A32_OP_UQSAX, + [PVM_A32_OP_UQSUB8] = &&PVM_A32_OP_UQSUB8, + [PVM_A32_OP_UQSUB16] = &&PVM_A32_OP_UQSUB16, + [PVM_A32_OP_SHADD8] = &&PVM_A32_OP_SHADD8, + [PVM_A32_OP_SHADD16] = &&PVM_A32_OP_SHADD16, + [PVM_A32_OP_SHASX] = &&PVM_A32_OP_SHASX, + [PVM_A32_OP_SHSAX] = &&PVM_A32_OP_SHSAX, + [PVM_A32_OP_SHSUB8] = &&PVM_A32_OP_SHSUB8, + [PVM_A32_OP_SHSUB16] = &&PVM_A32_OP_SHSUB16, + [PVM_A32_OP_UHADD8] = &&PVM_A32_OP_UHADD8, + [PVM_A32_OP_UHADD16] = &&PVM_A32_OP_UHADD16, + [PVM_A32_OP_UHASX] = &&PVM_A32_OP_UHASX, + [PVM_A32_OP_UHSAX] = &&PVM_A32_OP_UHSAX, + [PVM_A32_OP_UHSUB8] = &&PVM_A32_OP_UHSUB8, + [PVM_A32_OP_UHSUB16] = &&PVM_A32_OP_UHSUB16, + [PVM_A32_OP_QADD] = &&PVM_A32_OP_QADD, + [PVM_A32_OP_QSUB] = &&PVM_A32_OP_QSUB, + [PVM_A32_OP_QDADD] = &&PVM_A32_OP_QDADD, + [PVM_A32_OP_QDSUB] = &&PVM_A32_OP_QDSUB, + [PVM_A32_OP_MRS] = &&PVM_A32_OP_MRS, + [PVM_A32_OP_MSR_IMM] = &&PVM_A32_OP_MSR_IMM, + [PVM_A32_OP_MSR_REG] = &&PVM_A32_OP_MSR_REG, + [PVM_A32_OP_STOP] = &&PVM_A32_OP_STOP, diff --git a/src/jit/interpreter/arm32/handlers.inc b/src/jit/interpreter/arm32/handlers.inc index 06742d7..241fcfb 100644 --- a/src/jit/interpreter/arm32/handlers.inc +++ b/src/jit/interpreter/arm32/handlers.inc @@ -1249,7 +1249,7 @@ HANDLER(PVM_A32_OP_MSR_REG): { } HANDLER(PVM_A32_OP_STOP): { - // TODO: Implement handler for PVM_A32_OP_STOP - DISPATCH(); + printf("IT WORKS!\n"); + return; } diff --git a/src/jit/interpreter/arm32/instruction.c b/src/jit/interpreter/arm32/instruction.c index f2a7a32..a08c1eb 100644 --- a/src/jit/interpreter/arm32/instruction.c +++ b/src/jit/interpreter/arm32/instruction.c @@ -1,47 +1,101 @@ /* - * THIS FILE IS A WORK IN PROGRESS AND WILL BE RE-WRITTEN - * Defines pvm_jit_interpreter_instruction_t struct and its internal opcodes. + * Defines pvm_jit_interpreter_arm32_instruction_t struct and its internal + * opcodes. */ #include "frontend/decoder/arm32_opcodes.h" +#include "common/passert.h" #include +#include +#include + +/* + * Computed gotos are a GCC/Clang extension that significantly improves + * interpreter performance by predicting branch targets. + */ #if defined(__GNUC__) || defined(__clang__) - #define HANDLER(name) HANDLER_##name - #define DISPATCH() do { \ - instr++; \ - goto *dispatch_table[instr->opcode]; \ - } while(0) +#define PVM_USE_COMPUTED_GOTO 1 #else - #define HANDLER(name) case name - #define DISPATCH() goto dispatch_loop +#define PVM_USE_COMPUTED_GOTO 0 #endif +typedef struct +{ + uint32_t GPRs[16]; + uint32_t PSTATE; +} pvm_jit_interpreter_arm32_cpu_state_t; + typedef struct { pvm_jit_decoder_arm32_opcode_t opcode; -} instruction_t; +} pvm_jit_interpreter_arm32_instruction_t; void -temp(void) +temp (void) { - instruction_t *instr = malloc(sizeof(*instr)); - instr->opcode = PVM_A32_OP_STOP; -#if defined(__GNUC__) || defined(__clang__) - static const void* const dispatch_table[] = { - #include "handler_table.inc" + pvm_jit_interpreter_arm32_instruction_t *instr = calloc(3, sizeof(*instr)); + instr->opcode = PVM_A32_OP_ADD_REG; + (++instr)->opcode = PVM_A32_OP_STOP; +/* + * Uses a jump table with address labels (&&LABEL) to dispatch directly to the + * handler. + */ +#if PVM_USE_COMPUTED_GOTO + + /* The dispatch table contains the address of every label in handlers.inc */ + static const void *const dispatch_table[] = { +#include "handler_table.inc" }; - // Initial dispatch +/* + * HANDLER macro defines the label target. + * DISPATCH macro increments IP and jumps to the next handler. + */ +#define HANDLER(name) name +#define DISPATCH() \ + do \ + { \ + instr++; \ + goto *dispatch_table[instr->opcode]; \ +} while (0) + + + /* Must perform the initial jump to start the race. */ goto *dispatch_table[instr->opcode]; + + +/* Include the instruction logic */ +#include "handlers.inc" + +#undef HANDLER +#undef DISPATCH + +/* + * Uses a standard switch statement. Slower due to bounds checking and lack of + * branch prediction, but 100% portable and safe. + */ #else - dispatch_loop: - switch (instr->opcode) { -#endif - #include "handlers.inc" +/* + * HANDLER macro defines a switch case. + * DISPATCH macro jumps back to the switch statement. + */ +#define HANDLER(name) case name +#define DISPATCH() goto dispatch_loop -#if !defined(__GNUC__) && !defined(__clang__) - default: goto HANDLER_PVM_A32_OP_STOP; +dispatch_loop: + switch (instr->opcode) + { +/* Include the instruction logic */ +#include "handlers.inc" + + default: + PVM_ASSERT_MSG( + 0, "Invalid Opcode in interpreter dispatch: %d", instr->opcode); + break; } + +#undef HANDLER +#undef DISPATCH #endif } diff --git a/src/jit/interpreter/arm32/instruction.h b/src/jit/interpreter/arm32/instruction.h new file mode 100644 index 0000000..0fbdede --- /dev/null +++ b/src/jit/interpreter/arm32/instruction.h @@ -0,0 +1 @@ +void temp(void);