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To handle faults such as data aborts, alignment faults, or supervisor
calls, the CPU must transition from the guest's context into a
privileged exception handler. This patch emulates the hardware sequence
for this entry process.
1. The vcpu_state_t struct includes the essential EL1 system registers
required for exception handling (ELR_EL1, SPSR_EL1, ESR_EL1, FAR_EL1,
and VBAR_EL1).
2. A new function, take_synchronous_exception(), is introduced. It
models the requirements for entering an exception targeting EL1:
- Saves the return address (PC) into ELR_EL1.
- Saves the current proccess state (PSTATE) into SPSR_EL1.
- Contructs the Exception Syndrome Register (ESR_EL1) from the
provided Exception Class and ISS.
- Saves the faulting address to FAR_EL1 for data aborts.
- Updates the live PSTATE to a safe state for the handler.
This implementation is intentially partial. The final step of updating the
PC to jump to a handler in the guest's vector table (using VBAR_EL1) is
stubbed out. The vector table will contain assembly instructions so a
functional instruction decoder is required to fully complete the
exception handler.
Signed-off-by: Ronald Caesar <github43132@proton.me>
7 lines
121 B
C++
7 lines
121 B
C++
#include "memory.h"
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#include "Base/Assert.h"
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namespace pound::aarch64::memory
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{
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} // namespace pound::aarch64::memory
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