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https://github.com/pound-emu/pound.git
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167 lines
8 KiB
C++
167 lines
8 KiB
C++
#include "isa.h"
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#include "guest.h"
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#include "memory/arena.h"
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#include <cassert>
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namespace pound::arm64
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{
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void take_synchronous_exception(vcpu_state_t* vcpu, uint8_t exception_class, uint32_t iss, uint64_t faulting_address)
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{
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assert(nullptr != vcpu);
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/* An EC holds 6 bits.*/
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assert(0 == (exception_class & 11000000));
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/* An ISS holds 25 bits */
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assert(0 == (iss & 0xFE000000));
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vcpu->elr_el1 = vcpu->pc;
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vcpu->spsr_el1 = vcpu->pstate;
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vcpu->esr_el1 = 0;
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/* Bits [31:26] are the Exception Class (EC). */
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/* Bits [25] is the Instruction Length (IL), 1 for a 32-bit instruction. */
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/* Bits [24:0] are the Instruction Specific Syndrome (ISS) */
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const uint64_t esr_il_bit = (1ULL << 25);
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vcpu->esr_el1 = ((uint64_t)exception_class << 26) | esr_il_bit | iss;
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if ((exception_class == EC_DATA_ABORT) || (exception_class == EC_DATA_ABORT_LOWER_EL))
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{
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vcpu->far_el1 = faulting_address;
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}
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/* The CPU state must be changed to a known safe state for handling */
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vcpu->pstate &= ~0xF0000000;
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/* Mask asynchronous exceptions (IRQ, FIQ, SError). We dont want the
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* Exception handler to be interruoted by a less important event. */
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const uint32_t PSTATE_IRQ_BIT = (1 << 7);
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const uint32_t PSTATE_FIQ_BIT = (1 << 6);
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const uint32_t PSTATE_SERROR_BIT = (1 << 8);
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vcpu->pstate |= (PSTATE_IRQ_BIT | PSTATE_FIQ_BIT | PSTATE_SERROR_BIT);
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/* Set the target exception level to EL1. The mode field M[3:0] is set
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* to 0b0101 for EL1h (using SP_EL1). (page 913 in manual) */
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const uint32_t PSTATE_EL_MASK = 0b1111;
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vcpu->pstate &= ~PSTATE_EL_MASK;
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const uint32_t PSTATE_EL1H = 0b0101;
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vcpu->pstate |= PSTATE_EL1H;
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/* TODO(GloriousTacoo:arm): DO NOT IMPLEMENT UNTIL THE INSTRUCTION
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* DECODER IS FINISHED.
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*
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* Create an Exception Vector Table, determine
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* the address of the exception handler, then update the PC.
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*
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* vcpu->pc = vcpu->vbar_el1 + offset; */
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}
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/** THIS FUNCTION WAS MADE WITH AI AND IS CALLED WHEN RUNNING THE CPU TEST FROM THE GUI!
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*
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* @brief Runs a comprehensive suite of tests on the guest memory access functions using the project's logging system.
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*
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* This function systematically tests the read and write capabilities of the memory
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* subsystem for all standard data sizes (8, 16, 32, and 64 bits). It verifies
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* that data written to memory can be correctly read back.
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*
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* It specifically checks:
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* 1. A standard aligned address in the middle of RAM.
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*
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* @param memory A pointer to an initialized guest_memory_t struct.
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* @return true if all tests pass, false otherwise.
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*/
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bool test_guest_ram_access(pound::arm64::memory::guest_memory_t* memory)
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{
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LOG_INFO(Memory, "--- [ Starting Guest RAM Access Test ] ---");
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if (memory == nullptr || memory->base == nullptr || memory->size < 4096)
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{
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LOG_CRITICAL(Memory, "Invalid memory block provided. Cannot run tests.");
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return false;
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}
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bool all_tests_passed = true;
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#define RUN_TEST(description, condition) \
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do \
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{ \
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char log_buffer[256]; \
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if (condition) \
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{ \
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snprintf(log_buffer, sizeof(log_buffer), " [TEST] %-45s... [PASS]", description); \
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LOG_INFO(Memory, log_buffer); \
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} \
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else \
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{ \
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snprintf(log_buffer, sizeof(log_buffer), " [TEST] %-45s... [FAIL]", description); \
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LOG_ERROR(Memory, log_buffer); \
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all_tests_passed = false; \
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} \
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} while (0)
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#define VERIFY_ACCESS(size, suffix, addr, write_val) \
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do \
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{ \
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guest_mem_write##suffix(memory, addr, write_val); \
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uint##size##_t read_val = guest_mem_read##suffix(memory, addr); \
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bool success = (read_val == write_val); \
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RUN_TEST("Write/Read " #size "-bit", success); \
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if (!success) \
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{ \
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char error_buffer[256]; \
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snprintf(error_buffer, sizeof(error_buffer), " -> At GPA 0x%016llx, Expected 0x%016llx, Got 0x%016llx", \
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(unsigned long long)addr, (unsigned long long)write_val, (unsigned long long)read_val); \
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LOG_ERROR(Memory, error_buffer); \
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} \
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} while (0)
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// --- 1. Test a typical, aligned address in the middle of memory ---
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LOG_INFO(Memory, "[INFO] Testing standard access at a midrange address (GPA 0x1000)...");
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uint64_t test_addr = 0x1000;
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VERIFY_ACCESS(8, b, test_addr + 0, 0xA5);
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VERIFY_ACCESS(16, w, test_addr + 2, 0xBEEF);
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VERIFY_ACCESS(32, l, test_addr + 4, 0xDEADBEEF);
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VERIFY_ACCESS(64, q, test_addr + 8, 0xCAFEBABE01234567);
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// --- 2. Test the very beginning of the memory block ---
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LOG_INFO(Memory, "[INFO] Testing boundary access at the start of RAM (GPA 0x0)...");
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VERIFY_ACCESS(64, q, 0x0, 0xFEEDFACEDEADBEEF);
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// --- 3. Test the very end of the memory block ---
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LOG_INFO(Memory, "[INFO] Testing boundary access at the end of RAM...");
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uint64_t end_addr_b = memory->size - 1;
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uint64_t end_addr_w = (memory->size - 2) & ~1ULL;
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uint64_t end_addr_l = (memory->size - 4) & ~3ULL;
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uint64_t end_addr_q = (memory->size - 8) & ~7ULL;
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VERIFY_ACCESS(8, b, end_addr_b, 0xFE);
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VERIFY_ACCESS(16, w, end_addr_w, 0xFEFE);
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VERIFY_ACCESS(32, l, end_addr_l, 0xFEFEFEFE);
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VERIFY_ACCESS(64, q, end_addr_q, 0xFEFEFEFEFEFEFEFE);
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// --- 4. Final Verdict ---
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LOG_INFO(Memory, "--- [ Guest RAM Access Test Finished ] ---");
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if (all_tests_passed)
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{
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LOG_INFO(Memory, ">>> Result: ALL TESTS PASSED");
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}
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else
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{
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LOG_ERROR(Memory, ">>> Result: SOME TESTS FAILED");
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}
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LOG_INFO(Memory, "----------------------------------------------");
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return all_tests_passed;
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}
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void cpuTest()
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{
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vcpu_state_t vcpu_states[CPU_CORES] = {};
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pound::memory::arena_t guest_memory_arena = pound::memory::arena_init(GUEST_RAM_SIZE);
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assert(nullptr != guest_memory_arena.data);
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pound::arm64::memory::guest_memory_t guest_ram = {};
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guest_ram.base = static_cast<uint8_t*>(guest_memory_arena.data);
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guest_ram.size = guest_memory_arena.capacity;
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(void)test_guest_ram_access(&guest_ram);
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}
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} // namespace pound::armv64
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