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cc2fb074e3
Pound's asserts were broken from the very beginning and I've just realized this. Fixing it is not my problem. Signed-off-by: Ronald Caesar <github43132@proton.me>
127 lines
4.3 KiB
C++
127 lines
4.3 KiB
C++
// Copyright 2025 Pound Emulator Project. All rights reserved.
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#pragma once
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#include <cstdlib>
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#include <cstring>
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#include "Base/Logging/Log.h"
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namespace pound::arm64
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{
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/* AArch64 R0-R31 */
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#define GP_REGISTERS 32
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/* AArch64 V0-V31 */
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#define FP_REGISTERS 32
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#define CACHE_LINE_SIZE 64
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#define GUEST_RAM_SIZE 10240 // 10KiB
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#define CPU_CORES 8
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/* Data Abort exception taken without a change in Exception level. */
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#define EC_DATA_ABORT 0b100101
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/* Data Abort exception from a lower Exception level. */
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#define EC_DATA_ABORT_LOWER_EL 0b100100
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/*
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* vcpu_state_t - Holds the architectural and selected system-register state for an emulated vCPU.
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* @v: 128-bit SIMD/FP vector registers V0–V31.
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* @r: General-purpose registers X0–X31 (X31 as SP/ZR as appropriate).
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* @pc: Program Counter.
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* @cntfreq_el0: Counter Frequency.
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* @cntpct_el0: Physical Counter.
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* @cntvct_el0: Virtual Counter - CRITICAL for timing.
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* @cntv_cval_el0: Virtual Timer Compare Value.
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* @pmccntr_el0: Cycle Counter.
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* @tpidr_el0: Thread Pointer ID Register.
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* @tpidrro_el0: Thread Pointer ID, read-only.
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* @elr_el1: Exception Link Register.
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* @esr_el1: Exception Syndrome Register.
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* @far_el1: Fault Address Register.
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* @vbar_el1: Vector Base Address Register.
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* @sctlr_el1: System Control Register.
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* @spsr_el1: Saved Program Status Register.
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* @ctr_el0: Cache-Type.
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* @cntv_ctl_el0: Virtual Timer Control.
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* @dczid_el0: Data Cache Zero ID.
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* @pmcr_el0: Performance Monitor Counter.
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* @pstate: Process State Register (NZCV, DAIF, EL, etc.).
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*
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* This structure is aligned to the L1 cache line size to prevent false sharing
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* when multiple host threads are emulating vCPUs on different physical cores.
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*/
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typedef struct alignas(CACHE_LINE_SIZE)
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{
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unsigned __int128 v[FP_REGISTERS];
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uint64_t r[GP_REGISTERS];
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uint64_t pc;
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uint64_t cntfreq_el0;
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uint64_t cntpct_el0;
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uint64_t cntvct_el0;
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uint64_t cntv_cval_el0;
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uint64_t pmccntr_el0;
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uint64_t tpidr_el0;
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uint64_t tpidrro_el0;
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/*
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* Stores the Program Counter of the instruction that was interrupted.
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* For a synchronous fault, it's the address of the faulting instruction
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* itself.
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*/
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uint64_t elr_el1;
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/*
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* Tells the guest OS why the exception happened. It contains a high
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* level Exception Class (EC) (eg, Data Abort) and a low level
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* Instruction Specific Syndrome (ISS) with fine-grained details.
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* (eg, it was an allignment fault cause by a write operation.)
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*/
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uint64_t esr_el1;
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/* The memory address that caused a Data Abort exception. */
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uint64_t far_el1;
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/* SCTLR_EL1[0] bit enables the MMU. */
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uint64_t sctlr_el1;
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/*
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* A snapshot of the current PSTATE register before the exception.
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* This is for restoring the program's state when returning from an
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* exception.
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*/
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uint64_t spsr_el1;
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/*
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* The base address in guest memory where the Exception Vector Table
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* can be found.
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*/
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uint64_t vbar_el1;
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uint32_t ctr_el0;
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uint32_t cntv_ctl_el0;
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uint32_t dczid_el0;
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uint32_t pmcr_el0;
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uint32_t pstate;
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} vcpu_state_t;
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/*
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* take_synchronous_exception() - Emulates the hardware process of taking a synchronous exception to EL1.
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*
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* @vcpu: A pointer to the vCPU state to be modified.
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* @exception_class: The high-level Exception Class (EC) code for ESR_EL1.
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* @iss: The low-level Instruction Specific Syndrome (ISS) code for ESR_EL1.
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* @faulting_address: The faulting address, to be written to FAR_EL1. Only valid for Data/Instruction Aborts. Pass 0 for other exception types.
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*
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* This function modifies the vCPU state according to the rules for taking a
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* synchronous exception from a lower or same exception level that is targeting EL1.
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* It saves the necessary return state, populates the syndrome registers,
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* updates the processor state for entry into EL1, and calculates the new
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* program counter by branching to the appropriate offset in the EL1 vector table.
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*
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*/
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void take_synchronous_exception(vcpu_state_t* vcpu, uint8_t exception_class, uint32_t iss, uint64_t faulting_address);
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void cpuTest();
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} // namespace pound::arm64
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