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63 commits 11 branches 644 tags 195 MiB
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4 commits

Author SHA1 Message Date
gdkchan
b4a1cfde10 Add SMULL (vector), USHR (scalar), FCCMPE, FNMSUB, fixed a some instructions 2018-02-20 14:39:03 -03:00
gdkchan
3872ae034d Add MLS (vector) instruction, fix mistake introduced on last commit 2018-02-18 02:13:42 -03:00
gdkchan
595e7ee588 Add FCVTAS and FCVTAU instructions 2018-02-17 18:59:37 -03:00
gdkchan
161193e113 CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements 2018-02-17 18:06:11 -03:00