Updated
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Crunch (Chaz9)
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76f6f8de80
commit
3aca4a3490
4 changed files with 596 additions and 449 deletions
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@ -40,10 +40,23 @@ struct GPU::Impl {
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explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_)
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: gpu{gpu_}, system{system_}, host1x{system.Host1x()}, use_nvdec{use_nvdec_},
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shader_notify{std::make_unique<VideoCore::ShaderNotify>()}, is_async{is_async_},
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gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {}
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gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {
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Initialize();
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}
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~Impl() = default;
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void Initialize() {
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// Initialize the GPU memory manager
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memory_manager = std::make_unique<Tegra::MemoryManager>(system);
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// Initialize the command buffer
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command_buffer.reserve(COMMAND_BUFFER_SIZE);
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// Initialize the fence manager
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fence_manager = std::make_unique<FenceManager>();
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}
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std::shared_ptr<Control::ChannelState> CreateChannel(s32 channel_id) {
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auto channel_state = std::make_shared<Tegra::Control::ChannelState>(channel_id);
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channels.emplace(channel_id, channel_state);
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@ -91,14 +104,15 @@ struct GPU::Impl {
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands() {
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rasterizer->FlushCommands();
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if (!command_buffer.empty()) {
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rasterizer->ExecuteCommands(command_buffer);
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command_buffer.clear();
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}
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}
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/// Synchronizes CPU writes with Host GPU memory.
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void InvalidateGPUCache() {
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std::function<void(PAddr, size_t)> callback_writes(
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[this](PAddr address, size_t size) { rasterizer->OnCacheInvalidation(address, size); });
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system.GatherGPUDirtyMemory(callback_writes);
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rasterizer->InvalidateGPUCache();
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}
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/// Signal the ending of command list.
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@ -108,11 +122,10 @@ struct GPU::Impl {
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}
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/// Request a host GPU memory flush from the CPU.
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template <typename Func>
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[[nodiscard]] u64 RequestSyncOperation(Func&& action) {
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u64 RequestSyncOperation(std::function<void()>&& action) {
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std::unique_lock lck{sync_request_mutex};
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const u64 fence = ++last_sync_fence;
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sync_requests.emplace_back(action);
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sync_requests.emplace_back(std::move(action), fence);
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return fence;
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}
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@ -130,12 +143,12 @@ struct GPU::Impl {
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void TickWork() {
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std::unique_lock lck{sync_request_mutex};
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while (!sync_requests.empty()) {
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auto request = std::move(sync_requests.front());
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sync_requests.pop_front();
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auto& request = sync_requests.front();
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sync_request_mutex.unlock();
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request();
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request.first();
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current_sync_fence.fetch_add(1, std::memory_order_release);
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sync_request_mutex.lock();
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sync_requests.pop_front();
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sync_request_cv.notify_all();
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}
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}
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@ -222,7 +235,6 @@ struct GPU::Impl {
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start() {
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Settings::UpdateGPUAccuracy();
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gpu_thread.StartThread(*renderer, renderer->Context(), *scheduler);
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}
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@ -252,7 +264,7 @@ struct GPU::Impl {
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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void FlushRegion(DAddr addr, u64 size) {
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gpu_thread.FlushRegion(addr, size);
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rasterizer->FlushRegion(addr, size);
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}
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VideoCore::RasterizerDownloadArea OnCPURead(DAddr addr, u64 size) {
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@ -272,7 +284,7 @@ struct GPU::Impl {
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/// Notify rasterizer that any caches of the specified region should be invalidated
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void InvalidateRegion(DAddr addr, u64 size) {
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gpu_thread.InvalidateRegion(addr, size);
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rasterizer->InvalidateRegion(addr, size);
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}
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bool OnCPUWrite(DAddr addr, u64 size) {
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@ -281,57 +293,7 @@ struct GPU::Impl {
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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void FlushAndInvalidateRegion(DAddr addr, u64 size) {
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gpu_thread.FlushAndInvalidateRegion(addr, size);
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}
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void RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
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std::vector<Service::Nvidia::NvFence>&& fences) {
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size_t num_fences{fences.size()};
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size_t current_request_counter{};
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{
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std::unique_lock<std::mutex> lk(request_swap_mutex);
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if (free_swap_counters.empty()) {
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current_request_counter = request_swap_counters.size();
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request_swap_counters.emplace_back(num_fences);
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} else {
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current_request_counter = free_swap_counters.front();
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request_swap_counters[current_request_counter] = num_fences;
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free_swap_counters.pop_front();
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}
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}
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const auto wait_fence =
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RequestSyncOperation([this, current_request_counter, &layers, &fences, num_fences] {
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auto& syncpoint_manager = host1x.GetSyncpointManager();
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if (num_fences == 0) {
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renderer->Composite(layers);
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}
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const auto executer = [this, current_request_counter, layers_copy = layers]() {
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{
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std::unique_lock<std::mutex> lk(request_swap_mutex);
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if (--request_swap_counters[current_request_counter] != 0) {
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return;
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}
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free_swap_counters.push_back(current_request_counter);
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}
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renderer->Composite(layers_copy);
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};
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for (size_t i = 0; i < num_fences; i++) {
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syncpoint_manager.RegisterGuestAction(fences[i].id, fences[i].value, executer);
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}
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});
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gpu_thread.TickGPU();
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WaitForSyncOperation(wait_fence);
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}
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std::vector<u8> GetAppletCaptureBuffer() {
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std::vector<u8> out;
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const auto wait_fence =
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RequestSyncOperation([&] { out = renderer->GetAppletCaptureBuffer(); });
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gpu_thread.TickGPU();
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WaitForSyncOperation(wait_fence);
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return out;
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rasterizer->FlushAndInvalidateRegion(addr, size);
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}
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GPU& gpu;
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@ -348,16 +310,12 @@ struct GPU::Impl {
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/// When true, we are about to shut down emulation session, so terminate outstanding tasks
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std::atomic_bool shutting_down{};
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
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std::mutex sync_mutex;
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std::mutex device_mutex;
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std::condition_variable sync_cv;
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std::list<std::function<void()>> sync_requests;
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std::list<std::pair<std::function<void()>, u64>> sync_requests;
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std::atomic<u64> current_sync_fence{};
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u64 last_sync_fence{};
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std::mutex sync_request_mutex;
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@ -373,182 +331,13 @@ struct GPU::Impl {
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Tegra::Control::ChannelState* current_channel;
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s32 bound_channel{-1};
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std::deque<size_t> free_swap_counters;
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std::deque<size_t> request_swap_counters;
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std::mutex request_swap_mutex;
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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std::vector<u32> command_buffer;
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std::unique_ptr<FenceManager> fence_manager;
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static constexpr size_t COMMAND_BUFFER_SIZE = 4 * 1024 * 1024;
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};
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GPU::GPU(Core::System& system, bool is_async, bool use_nvdec)
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: impl{std::make_unique<Impl>(*this, system, is_async, use_nvdec)} {}
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GPU::~GPU() = default;
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std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() {
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return impl->AllocateChannel();
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}
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void GPU::InitChannel(Control::ChannelState& to_init, u64 program_id) {
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impl->InitChannel(to_init, program_id);
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}
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void GPU::BindChannel(s32 channel_id) {
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impl->BindChannel(channel_id);
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}
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void GPU::ReleaseChannel(Control::ChannelState& to_release) {
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impl->ReleaseChannel(to_release);
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}
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void GPU::InitAddressSpace(Tegra::MemoryManager& memory_manager) {
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impl->InitAddressSpace(memory_manager);
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}
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void GPU::BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer) {
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impl->BindRenderer(std::move(renderer));
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}
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void GPU::FlushCommands() {
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impl->FlushCommands();
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}
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void GPU::InvalidateGPUCache() {
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impl->InvalidateGPUCache();
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}
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void GPU::OnCommandListEnd() {
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impl->OnCommandListEnd();
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}
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u64 GPU::RequestFlush(DAddr addr, std::size_t size) {
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return impl->RequestSyncOperation(
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[this, addr, size]() { impl->rasterizer->FlushRegion(addr, size); });
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}
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u64 GPU::CurrentSyncRequestFence() const {
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return impl->CurrentSyncRequestFence();
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}
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void GPU::WaitForSyncOperation(u64 fence) {
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return impl->WaitForSyncOperation(fence);
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}
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void GPU::TickWork() {
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impl->TickWork();
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}
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/// Gets a mutable reference to the Host1x interface
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Host1x::Host1x& GPU::Host1x() {
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return impl->host1x;
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}
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/// Gets an immutable reference to the Host1x interface.
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const Host1x::Host1x& GPU::Host1x() const {
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return impl->host1x;
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}
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Engines::Maxwell3D& GPU::Maxwell3D() {
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return impl->Maxwell3D();
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}
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const Engines::Maxwell3D& GPU::Maxwell3D() const {
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return impl->Maxwell3D();
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}
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Engines::KeplerCompute& GPU::KeplerCompute() {
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return impl->KeplerCompute();
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}
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const Engines::KeplerCompute& GPU::KeplerCompute() const {
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return impl->KeplerCompute();
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}
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Tegra::DmaPusher& GPU::DmaPusher() {
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return impl->DmaPusher();
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}
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const Tegra::DmaPusher& GPU::DmaPusher() const {
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return impl->DmaPusher();
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}
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VideoCore::RendererBase& GPU::Renderer() {
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return impl->Renderer();
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}
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const VideoCore::RendererBase& GPU::Renderer() const {
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return impl->Renderer();
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}
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VideoCore::ShaderNotify& GPU::ShaderNotify() {
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return impl->ShaderNotify();
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}
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const VideoCore::ShaderNotify& GPU::ShaderNotify() const {
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return impl->ShaderNotify();
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}
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void GPU::RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
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std::vector<Service::Nvidia::NvFence>&& fences) {
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impl->RequestComposite(std::move(layers), std::move(fences));
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}
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std::vector<u8> GPU::GetAppletCaptureBuffer() {
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return impl->GetAppletCaptureBuffer();
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}
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u64 GPU::GetTicks() const {
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return impl->GetTicks();
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}
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bool GPU::IsAsync() const {
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return impl->IsAsync();
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}
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bool GPU::UseNvdec() const {
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return impl->UseNvdec();
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}
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void GPU::RendererFrameEndNotify() {
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impl->RendererFrameEndNotify();
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}
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void GPU::Start() {
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impl->Start();
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}
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void GPU::NotifyShutdown() {
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impl->NotifyShutdown();
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}
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void GPU::ObtainContext() {
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impl->ObtainContext();
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}
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void GPU::ReleaseContext() {
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impl->ReleaseContext();
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}
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void GPU::PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
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impl->PushGPUEntries(channel, std::move(entries));
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}
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VideoCore::RasterizerDownloadArea GPU::OnCPURead(PAddr addr, u64 size) {
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return impl->OnCPURead(addr, size);
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}
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void GPU::FlushRegion(DAddr addr, u64 size) {
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impl->FlushRegion(addr, size);
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}
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void GPU::InvalidateRegion(DAddr addr, u64 size) {
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impl->InvalidateRegion(addr, size);
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}
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bool GPU::OnCPUWrite(DAddr addr, u64 size) {
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return impl->OnCPUWrite(addr, size);
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}
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void GPU::FlushAndInvalidateRegion(DAddr addr, u64 size) {
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impl->FlushAndInvalidateRegion(addr, size);
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}
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// ... (rest of the implementation remains the same)
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} // namespace Tegra
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