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base: mirrors:0d957968dfd50d785af504b5ec3f9520216fce4e
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mirrors:main
mirrors:arm64
mirrors:Xphalnos-arm64
mirrors:fs
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compare: mirrors:c508a927ea59b379b831ba69c4e1e9ef9641e965
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mirrors:arm64
mirrors:Xphalnos-arm64
mirrors:main
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No commits in common. "0d957968dfd50d785af504b5ec3f9520216fce4e" and "c508a927ea59b379b831ba69c4e1e9ef9641e965" have entirely different histories.
0d957968df ... c508a927ea

19 changed files with 431 additions and 3670 deletions
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8
CMakeLists.txt
View file

@ -104,11 +104,11 @@ set(GEN_TEST_SRC ${CMAKE_CURRENT_SOURCE_DIR}/tests/jit/decoder/test_arm32_genera
add_custom_command(
OUTPUT ${GEN_TEST_SRC}
COMMAND Python3::Interpreter ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_tests.py
${CMAKE_SOURCE_DIR}/src/jit/common/a32_instructions.inc
COMMAND Python3::Interpreter ${CMAKE_SOURCE_DIR}/scripts/generate_decoder_tests.py
${CMAKE_SOURCE_DIR}/src/jit/frontend/decoder/arm32.inc
${GEN_TEST_SRC}
DEPENDS ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_tests.py
${CMAKE_SOURCE_DIR}/src/jit/common/a32_instructions.inc
DEPENDS ${CMAKE_SOURCE_DIR}/scripts/generate_decoder_tests.py
${CMAKE_SOURCE_DIR}/src/jit/frontend/decoder/arm32.inc
COMMENT "Generating ARM32 Decoder Tests"
)

2
scripts/generate_jit_decoder_tests.py → scripts/generate_decoder_tests.py
View file

@ -82,7 +82,7 @@ from typing import List, Dict, Optional, Tuple
CPP_HEADER = """/*
* GENERATED FILE - DO NOT EDIT
*
* This file is generated by scripts/generate_jit_decoder_tests.py
* This file is generated by scripts/generate_decoder_tests.py
*
* PURPOSE:
* Provides 100% requirements-based test coverage for the ARM32 Instruction Decoder.

241
scripts/generate_jit_assets.py
View file

@ -1,241 +0,0 @@
#!/usr/bin/env python3
import re
import sys
import argparse
# Increased bucket size to handle overlapping wildcards
MAX_BUCKET_SIZE = 64
TABLE_SIZE = 4096
# Bits [27:20] and [7:4]
HASH_BITS_MASK = 0x0FF000F0
class Instruction:
def __init__(self, name, mnemonic, bitstring, array_index):
self.name = name
self.mnemonic = mnemonic
self.bitstring = bitstring
self.array_index = array_index
self.mask = 0
self.expected = 0
self.parse_bits()
def parse_bits(self):
if len(self.bitstring) != 32:
print(
f"Error: Bitstring length {len(self.bitstring)} invalid for {self.name}"
)
sys.exit(1)
for i, char in enumerate(self.bitstring):
bit_pos = 31 - i
if char == "0":
self.mask |= 1 << bit_pos
elif char == "1":
self.mask |= 1 << bit_pos
self.expected |= 1 << bit_pos
# Variable bits (c, n, d, m, etc) leave mask as 0
def parse_inc_file(input_path):
instructions = []
regex = re.compile(r'INST\(\s*([A-Za-z0-9_]+),\s*"(.*?)",\s*"(.*?)"\s*\)')
try:
with open(input_path, "r") as f:
lines = f.readlines()
except FileNotFoundError:
print(f"Error: Could not find input file: {input_path}")
sys.exit(1)
index_counter = 0
for line in lines:
line = line.strip()
if not line or line.startswith("//"):
continue
match = regex.search(line)
if match:
inst = Instruction(
match.group(1), match.group(2), match.group(3), index_counter
)
instructions.append(inst)
index_counter += 1
return instructions
def generate_lookup_table(instructions):
buckets = {i: [] for i in range(TABLE_SIZE)}
# Iterate over every possible hash index to determine which instructions belong in it
for i in range(TABLE_SIZE):
# Reconstruct the 32-bit value that would generate this hash index
# Hash algorithm: (Major << 4) | Minor
# Major is bits [27:20], Minor is bits [7:4]
major_val = (i >> 4) & 0xFF
minor_val = i & 0x0F
# Create a "Probe" value with the hash bits set
probe_val = (major_val << 20) | (minor_val << 4)
for inst in instructions:
# Check if this instruction matches this hash index.
# An instruction matches if its FIXED bits (mask) match the Probe bits
# for the specific positions used by the hash.
relevant_mask = inst.mask & HASH_BITS_MASK
relevant_expected = inst.expected & HASH_BITS_MASK
if (probe_val & relevant_mask) == relevant_expected:
buckets[i].append(inst)
if len(buckets[i]) > MAX_BUCKET_SIZE:
print(
f"FATAL ERROR: Bucket {i:#05x} overflowed! Size: {len(buckets[i])}"
)
print(
"This means too many instructions map to the same hash index."
)
sys.exit(1)
return buckets
def write_decoder_table_h_file(path):
print(f"Generating decoder table header file: {path}")
with open(path, "w") as f:
f.write("/* GENERATED FILE - DO NOT EDIT */\n")
f.write("/* This file is generated by scripts/generate_jit_assets.py */\n")
f.write("#ifndef POUND_JIT_DECODER_ARM32_GENERATED_H\n")
f.write("#define POUND_JIT_DECODER_ARM32_GENERATED_H\n\n")
f.write('#include "arm32.h"\n')
f.write("#include <stddef.h>\n\n")
f.write(f"#define LOOKUP_TABLE_MAX_BUCKET_SIZE {MAX_BUCKET_SIZE}U\n\n")
f.write("typedef struct {\n")
f.write(
" const pvm_jit_decoder_arm32_instruction_info_t *instructions[LOOKUP_TABLE_MAX_BUCKET_SIZE];\n"
)
f.write(" size_t count;\n")
f.write("} decode_bucket_t;\n\n")
f.write(
f"extern const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}];\n\n"
)
f.write("#endif\n")
def write_opcodes_header(path, instructions):
"""Generates the arm32_opcodes.h file with a unique enum for each mnemonic."""
print(f"Generating opcode header file: {path}")
seen = set()
with open(path, "w") as f:
f.write("/* GENERATED FILE - DO NOT EDIT */\n")
f.write("/* This file is generated by scripts/generate_jit_assets.py */\n")
f.write("#ifndef POUND_JIT_DECODER_ARM32_OPCODES_H\n")
f.write("#define POUND_JIT_DECODER_ARM32_OPCODES_H\n\n")
f.write("typedef enum {\n")
for inst in instructions:
enum_name = f" PVM_A32_OP_{inst.name.upper()},\n"
if enum_name not in seen:
f.write(enum_name)
seen.add(enum_name)
f.write(" PVM_A32_OP_STOP,\n")
f.write("} pvm_jit_decoder_arm32_opcode_t;\n\n")
f.write("#endif // POUND_JIT_DECODER_ARM32_OPCODES_H\n")
def write_decoder_table_c_file(path, instructions, buckets):
"""Writes the decoder C file, now including the opcode enum."""
print(f"Generating decoder table source file: {path}")
with open(path, "w") as f:
f.write("/* GENERATED FILE - DO NOT EDIT */\n")
f.write("/* This file is generated by scripts/generate_jit_assets.py */\n")
f.write('#include "arm32.h"\n')
f.write('#include "arm32_table.h"\n\n')
f.write(
f"static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[{len(instructions)}] = {{\n"
)
for inst in instructions:
f.write(
f' {{ "{inst.mnemonic}", "{inst.bitstring}", PVM_A32_OP_{inst.name.upper()}, {inst.mask:#010x}U, {inst.expected:#010x}U }},\n'
)
f.write("};\n")
f.write(f"const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}] = {{\n")
for i in range(TABLE_SIZE):
if len(buckets[i]) > 0:
f.write(f" [{i:#05x}] = {{ .instructions = {{ ")
for inst in buckets[i]:
f.write(f"&g_instructions[{inst.array_index}], ")
f.write(f"}}, .count = {len(buckets[i])}U }},\n")
f.write("};\n")
def write_interpreter_handler_table(path, instructions):
"""Generates the dispatch table."""
print(f"Generating interpreter handler table: {path}")
seen = set()
with open(path, "w") as f:
for inst in instructions:
enum_name = f"PVM_A32_OP_{inst.name.upper()}"
if enum_name not in seen:
f.write(f" [{enum_name}] = &&{enum_name},\n")
seen.add(enum_name)
f.write(f" [PVM_A32_OP_STOP] = &&PVM_A32_OP_STOP,\n")
def write_interpreter_handler_skeletons(path, instructions):
"""Generates a skeleton file for handlers."""
print(f"Generating new skeleton file: {path}")
seen = set()
with open(path, "w") as f:
f.write("/*\n")
f.write(" * GENERATED FILE - DO NOT EDIT\n")
f.write(" * This file is generated by scripts/generate_jit_assets.py \n")
f.write(
" * This file contains pre-generated, empty handler blocks for the every instruction.\n"
)
f.write(" */\n\n")
for inst in instructions:
enum_name = f"HANDLER(PVM_A32_OP_{inst.name.upper()}): {{\n"
if enum_name not in seen:
f.write(enum_name)
seen.add(enum_name)
f.write(f" // TODO: Implement handler for {inst.mnemonic}\n")
f.write(" DISPATCH();\n")
f.write("}\n\n")
f.write(f"HANDLER(PVM_A32_OP_STOP): {{\n")
f.write(f" // TODO: Implement handler for PVM_A32_OP_STOP\n")
f.write(" DISPATCH();\n")
f.write("}\n\n")
def main():
parser = argparse.ArgumentParser(description="Generate ARM32 Decoder Tables")
parser.add_argument("input")
parser.add_argument("--out-opcodes-h")
parser.add_argument("--out-decoder-c")
parser.add_argument("--out-decoder-h")
parser.add_argument("--out-handler-table-inc")
parser.add_argument("--out-handler-skeletons-inc")
args = parser.parse_args()
instructions = parse_inc_file(args.input)
buckets = generate_lookup_table(instructions)
# Generate all necessary files
write_opcodes_header(args.out_opcodes_h, instructions)
write_decoder_table_c_file(args.out_decoder_c, instructions, buckets)
write_decoder_table_h_file(args.out_decoder_h)
write_interpreter_handler_table(args.out_handler_table_inc, instructions)
write_interpreter_handler_skeletons(args.out_handler_skeletons_inc, instructions)
if __name__ == "__main__":
main()

147
scripts/generate_jit_decoder_a32_table.py Normal file
View file

@ -0,0 +1,147 @@
#!/usr/bin/env python3
import re
import sys
import argparse
# Increased bucket size to handle overlapping wildcards
MAX_BUCKET_SIZE = 64
TABLE_SIZE = 4096
# Bits [27:20] and [7:4]
HASH_BITS_MASK = 0x0FF000F0
class Instruction:
def __init__(self, name, mnemonic, bitstring, array_index):
self.name = name
self.mnemonic = mnemonic
self.bitstring = bitstring
self.array_index = array_index
self.mask = 0
self.expected = 0
self.parse_bits()
def parse_bits(self):
if len(self.bitstring) != 32:
print(f"Error: Bitstring length {len(self.bitstring)} invalid for {self.name}")
sys.exit(1)
for i, char in enumerate(self.bitstring):
bit_pos = 31 - i
if char == '0':
self.mask |= (1 << bit_pos)
elif char == '1':
self.mask |= (1 << bit_pos)
self.expected |= (1 << bit_pos)
# Variable bits (c, n, d, m, etc) leave mask as 0
def parse_inc_file(input_path):
instructions = []
regex = re.compile(r'INST\(\s*([A-Za-z0-9_]+),\s*"(.*?)",\s*"(.*?)"\s*\)')
try:
with open(input_path, 'r') as f:
lines = f.readlines()
except FileNotFoundError:
print(f"Error: Could not find input file: {input_path}")
sys.exit(1)
index_counter = 0
for line in lines:
line = line.strip()
if not line or line.startswith("//"):
continue
match = regex.search(line)
if match:
inst = Instruction(match.group(1), match.group(2), match.group(3), index_counter)
instructions.append(inst)
index_counter += 1
return instructions
def generate_lookup_table(instructions):
buckets = {i: [] for i in range(TABLE_SIZE)}
# Iterate over every possible hash index to determine which instructions belong in it
for i in range(TABLE_SIZE):
# Reconstruct the 32-bit value that would generate this hash index
# Hash algorithm: (Major << 4) | Minor
# Major is bits [27:20], Minor is bits [7:4]
major_val = (i >> 4) & 0xFF
minor_val = i & 0x0F
# Create a "Probe" value with the hash bits set
probe_val = (major_val << 20) | (minor_val << 4)
for inst in instructions:
# Check if this instruction matches this hash index.
# An instruction matches if its FIXED bits (mask) match the Probe bits
# for the specific positions used by the hash.
relevant_mask = inst.mask & HASH_BITS_MASK
relevant_expected = inst.expected & HASH_BITS_MASK
if (probe_val & relevant_mask) == relevant_expected:
buckets[i].append(inst)
if len(buckets[i]) > MAX_BUCKET_SIZE:
print(f"FATAL ERROR: Bucket {i:#05x} overflowed! Size: {len(buckets[i])}")
print("This means too many instructions map to the same hash index.")
sys.exit(1)
return buckets
def write_c_file(path, instructions, buckets):
with open(path, 'w') as f:
f.write("/* GENERATED FILE - DO NOT EDIT */\n")
f.write("/* This file is generated by scripts/generate_jit_decoder_a32_table.py */\n")
f.write('#include "arm32.h"\n')
f.write('#include "arm32_table_generated.h"\n\n')
f.write(f"static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[{len(instructions)}] = {{\n")
for inst in instructions:
f.write(f' {{ "{inst.mnemonic}", "{inst.bitstring}", {inst.mask:#010x}U, {inst.expected:#010x}U }},\n')
f.write("};\n\n")
f.write(f"const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}] = {{\n")
for i in range(TABLE_SIZE):
if len(buckets[i]) > 0:
f.write(f" [{i:#05x}] = {{ .instructions = {{ ")
for inst in buckets[i]:
f.write(f"&g_instructions[{inst.array_index}], ")
f.write(f"}}, .count = {len(buckets[i])}U }},\n")
f.write("};\n")
def write_h_file(path):
with open(path, 'w') as f:
f.write("#ifndef POUND_JIT_DECODER_ARM32_GENERATED_H\n")
f.write("#define POUND_JIT_DECODER_ARM32_GENERATED_H\n\n")
f.write('#include "arm32.h"\n')
f.write('#include <stddef.h>\n\n')
f.write(f"#define LOOKUP_TABLE_MAX_BUCKET_SIZE {MAX_BUCKET_SIZE}U\n\n")
f.write("typedef struct {\n")
f.write(" const pvm_jit_decoder_arm32_instruction_info_t *instructions[LOOKUP_TABLE_MAX_BUCKET_SIZE];\n")
f.write(" size_t count;\n")
f.write("} decode_bucket_t;\n\n")
f.write(f"extern const decode_bucket_t g_decoder_lookup_table[{TABLE_SIZE}];\n\n")
f.write("#endif\n")
# ---------------------------------------------------------
# Main Execution
# ---------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="Generate ARM32 Decoder Tables")
parser.add_argument("input", help="Path to arm32.inc")
parser.add_argument("out_c", help="Path to output .c file")
parser.add_argument("out_h", help="Path to output .h file")
args = parser.parse_args()
print(f"{args.input} -> {args.out_c}")
instructions = parse_inc_file(args.input)
buckets = generate_lookup_table(instructions)
write_c_file(args.out_c, instructions, buckets)
write_h_file(args.out_h)
if __name__ == "__main__":
main()

36
src/jit/CMakeLists.txt
View file

@ -1,30 +1,22 @@
# Define all the files that will be generated
set(GEN_OPCODES_H ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_opcodes.h)
set(GEN_DECODER_C ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table.c)
set(GEN_DECODER_H ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table.h)
set(GEN_HANDLER_TABLE ${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/handler_table.inc)
set(GEN_HANDLER_SKELETONS ${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/handlers.inc.skeleton)
set(INSTRUCTIONS ${CMAKE_CURRENT_SOURCE_DIR}/common/a32_instructions.inc)
set(SCRIPT ${CMAKE_SOURCE_DIR}/scripts/generate_jit_assets.py)
# Define the generated files
set(GEN_SOURCE ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table_generated.c)
set(GEN_HEADER ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table_generated.h)
set(INC_FILE ${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32.inc)
set(SCRIPT ${CMAKE_SOURCE_DIR}/scripts/generate_jit_decoder_a32_table.py)
add_custom_command(
OUTPUT ${GEN_OPCODES_H} ${GEN_DECODER_C} ${GEN_DECODER_H} ${GEN_HANDLER_TABLE} ${GEN_HANDLER_SKELETONS}
COMMAND Python3::Interpreter ${SCRIPT} ${INSTRUCTIONS}
--out-opcodes-h=${GEN_OPCODES_H}
--out-decoder-c=${GEN_DECODER_C}
--out-decoder-h=${GEN_DECODER_H}
--out-handler-table-inc=${GEN_HANDLER_TABLE}
--out-handler-skeletons-inc=${GEN_HANDLER_SKELETONS}
DEPENDS ${SCRIPT} ${INSTRUCTIONS}
COMMENT "Generating JIT assets"
OUTPUT ${GEN_SOURCE} ${GEN_HEADER}
COMMAND Python3::Interpreter ${SCRIPT} ${INC_FILE} ${GEN_SOURCE} ${GEN_HEADER}
DEPENDS ${SCRIPT} ${INC_FILE}
COMMENT "Generating ARM32 Decoder Tables"
)
add_library(jit STATIC)
target_sources(jit PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32.c
${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table.c
${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/instruction.c
${CMAKE_CURRENT_SOURCE_DIR}/frontend/decoder/arm32_table_generated.c
${CMAKE_CURRENT_SOURCE_DIR}/ir/type.c
${CMAKE_CURRENT_SOURCE_DIR}/ir/value.c
${CMAKE_CURRENT_SOURCE_DIR}/ir/opcode.c
@ -32,17 +24,11 @@ target_sources(jit PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/ir/basic_block.c
)
set_source_files_properties(
${CMAKE_CURRENT_SOURCE_DIR}/ir/opcode.c
PROPERTIES COMPILE_FLAGS "-Wno-c23-extensions -Wno-pedantic"
)
set_source_files_properties(
${CMAKE_CURRENT_SOURCE_DIR}/interpreter/arm32/instruction.c
PROPERTIES COMPILE_FLAGS "-Wno-gnu-label-as-value -Wno-unused-label"
)
target_link_libraries(jit PRIVATE common host)
target_include_directories(jit PUBLIC

2
src/jit/frontend/decoder/arm32.c
View file

@ -1,5 +1,5 @@
#include "arm32.h"
#include "arm32_table.h"
#include "arm32_table_generated.h"
#include "common/passert.h"
#include <string.h>
#include <stdbool.h>

6
src/jit/frontend/decoder/arm32.h
View file

@ -11,7 +11,6 @@
#ifndef POUND_JIT_DECODER_ARM32_H
#define POUND_JIT_DECODER_ARM32_H
#include "arm32_opcodes.h"
#include <stdint.h>
/* Extern C for unit tests. */
@ -23,9 +22,9 @@ extern "C" {
* instruction. */
typedef struct
{
/*! @brief The instruction mnemonic (e.g., "ADD", "LDR"). */
const char *name;
/*!
* @brief The raw bitstring representation.
* @details Used during initialization to calculate mask and expected
@ -33,9 +32,6 @@ typedef struct
*/
const char *bitstring;
/*! @brief The instruction's unique enum identifier. */
pvm_jit_decoder_arm32_opcode_t opcode;
/*!
* @brief The bitmask indicating which bits in the instruction word are
* significant.

0
src/jit/common/a32_instructions.inc → src/jit/frontend/decoder/arm32.inc
View file

260
src/jit/frontend/decoder/arm32_opcodes.h
View file

@ -1,260 +0,0 @@
/* GENERATED FILE - DO NOT EDIT */
/* This file is generated by scripts/generate_jit_assets.py */
#ifndef POUND_JIT_DECODER_ARM32_OPCODES_H
#define POUND_JIT_DECODER_ARM32_OPCODES_H
typedef enum {
PVM_A32_OP_DMB,
PVM_A32_OP_DSB,
PVM_A32_OP_ISB,
PVM_A32_OP_BLX_IMM,
PVM_A32_OP_BLX_REG,
PVM_A32_OP_B,
PVM_A32_OP_BL,
PVM_A32_OP_BX,
PVM_A32_OP_BXJ,
PVM_A32_OP_RFE,
PVM_A32_OP_SRS,
PVM_A32_OP_CPS,
PVM_A32_OP_SETEND,
PVM_A32_OP_CRC32,
PVM_A32_OP_CRC32C,
PVM_A32_OP_CDP,
PVM_A32_OP_MCR,
PVM_A32_OP_MCRR,
PVM_A32_OP_MRC,
PVM_A32_OP_MRRC,
PVM_A32_OP_LDC,
PVM_A32_OP_STC,
PVM_A32_OP_ADC_IMM,
PVM_A32_OP_ADC_REG,
PVM_A32_OP_ADC_RSR,
PVM_A32_OP_ADD_IMM,
PVM_A32_OP_ADD_REG,
PVM_A32_OP_ADD_RSR,
PVM_A32_OP_AND_IMM,
PVM_A32_OP_AND_REG,
PVM_A32_OP_AND_RSR,
PVM_A32_OP_BIC_IMM,
PVM_A32_OP_BIC_REG,
PVM_A32_OP_BIC_RSR,
PVM_A32_OP_CMN_IMM,
PVM_A32_OP_CMN_REG,
PVM_A32_OP_CMN_RSR,
PVM_A32_OP_CMP_IMM,
PVM_A32_OP_CMP_REG,
PVM_A32_OP_CMP_RSR,
PVM_A32_OP_EOR_IMM,
PVM_A32_OP_EOR_REG,
PVM_A32_OP_EOR_RSR,
PVM_A32_OP_MOV_IMM,
PVM_A32_OP_MOV_REG,
PVM_A32_OP_MOV_RSR,
PVM_A32_OP_MVN_IMM,
PVM_A32_OP_MVN_REG,
PVM_A32_OP_MVN_RSR,
PVM_A32_OP_ORR_IMM,
PVM_A32_OP_ORR_REG,
PVM_A32_OP_ORR_RSR,
PVM_A32_OP_RSB_IMM,
PVM_A32_OP_RSB_REG,
PVM_A32_OP_RSB_RSR,
PVM_A32_OP_RSC_IMM,
PVM_A32_OP_RSC_REG,
PVM_A32_OP_RSC_RSR,
PVM_A32_OP_SBC_IMM,
PVM_A32_OP_SBC_REG,
PVM_A32_OP_SBC_RSR,
PVM_A32_OP_SUB_IMM,
PVM_A32_OP_SUB_REG,
PVM_A32_OP_SUB_RSR,
PVM_A32_OP_TEQ_IMM,
PVM_A32_OP_TEQ_REG,
PVM_A32_OP_TEQ_RSR,
PVM_A32_OP_TST_IMM,
PVM_A32_OP_TST_REG,
PVM_A32_OP_TST_RSR,
PVM_A32_OP_BKPT,
PVM_A32_OP_SVC,
PVM_A32_OP_UDF,
PVM_A32_OP_SXTB,
PVM_A32_OP_SXTB16,
PVM_A32_OP_SXTH,
PVM_A32_OP_SXTAB,
PVM_A32_OP_SXTAB16,
PVM_A32_OP_SXTAH,
PVM_A32_OP_UXTB,
PVM_A32_OP_UXTB16,
PVM_A32_OP_UXTH,
PVM_A32_OP_UXTAB,
PVM_A32_OP_UXTAB16,
PVM_A32_OP_UXTAH,
PVM_A32_OP_PLD_IMM,
PVM_A32_OP_PLD_REG,
PVM_A32_OP_SEV,
PVM_A32_OP_SEVL,
PVM_A32_OP_WFE,
PVM_A32_OP_WFI,
PVM_A32_OP_YIELD,
PVM_A32_OP_NOP,
PVM_A32_OP_CLREX,
PVM_A32_OP_SWP,
PVM_A32_OP_SWPB,
PVM_A32_OP_STL,
PVM_A32_OP_STLEX,
PVM_A32_OP_STREX,
PVM_A32_OP_LDA,
PVM_A32_OP_LDAEX,
PVM_A32_OP_LDREX,
PVM_A32_OP_STLEXD,
PVM_A32_OP_STREXD,
PVM_A32_OP_LDAEXD,
PVM_A32_OP_LDREXD,
PVM_A32_OP_STLB,
PVM_A32_OP_STLEXB,
PVM_A32_OP_STREXB,
PVM_A32_OP_LDAB,
PVM_A32_OP_LDAEXB,
PVM_A32_OP_LDREXB,
PVM_A32_OP_STLH,
PVM_A32_OP_STLEXH,
PVM_A32_OP_STREXH,
PVM_A32_OP_LDAH,
PVM_A32_OP_LDAEXH,
PVM_A32_OP_LDREXH,
PVM_A32_OP_LDRBT,
PVM_A32_OP_LDRHT,
PVM_A32_OP_LDRSBT,
PVM_A32_OP_LDRSHT,
PVM_A32_OP_LDRT,
PVM_A32_OP_STRBT,
PVM_A32_OP_STRHT,
PVM_A32_OP_STRT,
PVM_A32_OP_LDR_LIT,
PVM_A32_OP_LDR_IMM,
PVM_A32_OP_LDR_REG,
PVM_A32_OP_LDRB_LIT,
PVM_A32_OP_LDRB_IMM,
PVM_A32_OP_LDRB_REG,
PVM_A32_OP_LDRD_LIT,
PVM_A32_OP_LDRD_IMM,
PVM_A32_OP_LDRD_REG,
PVM_A32_OP_LDRH_LIT,
PVM_A32_OP_LDRH_IMM,
PVM_A32_OP_LDRH_REG,
PVM_A32_OP_LDRSB_LIT,
PVM_A32_OP_LDRSB_IMM,
PVM_A32_OP_LDRSB_REG,
PVM_A32_OP_LDRSH_LIT,
PVM_A32_OP_LDRSH_IMM,
PVM_A32_OP_LDRSH_REG,
PVM_A32_OP_STR_IMM,
PVM_A32_OP_STR_REG,
PVM_A32_OP_STRB_IMM,
PVM_A32_OP_STRB_REG,
PVM_A32_OP_STRD_IMM,
PVM_A32_OP_STRD_REG,
PVM_A32_OP_STRH_IMM,
PVM_A32_OP_STRH_REG,
PVM_A32_OP_LDM,
PVM_A32_OP_LDMDA,
PVM_A32_OP_LDMDB,
PVM_A32_OP_LDMIB,
PVM_A32_OP_LDM_USR,
PVM_A32_OP_LDM_ERET,
PVM_A32_OP_STM,
PVM_A32_OP_STMDA,
PVM_A32_OP_STMDB,
PVM_A32_OP_STMIB,
PVM_A32_OP_STM_USR,
PVM_A32_OP_BFC,
PVM_A32_OP_BFI,
PVM_A32_OP_CLZ,
PVM_A32_OP_MOVT,
PVM_A32_OP_MOVW,
PVM_A32_OP_SBFX,
PVM_A32_OP_SEL,
PVM_A32_OP_UBFX,
PVM_A32_OP_USAD8,
PVM_A32_OP_USADA8,
PVM_A32_OP_PKHBT,
PVM_A32_OP_PKHTB,
PVM_A32_OP_RBIT,
PVM_A32_OP_REV,
PVM_A32_OP_REV16,
PVM_A32_OP_REVSH,
PVM_A32_OP_SSAT,
PVM_A32_OP_SSAT16,
PVM_A32_OP_USAT,
PVM_A32_OP_USAT16,
PVM_A32_OP_SDIV,
PVM_A32_OP_UDIV,
PVM_A32_OP_MLA,
PVM_A32_OP_MLS,
PVM_A32_OP_MUL,
PVM_A32_OP_SMLAL,
PVM_A32_OP_SMULL,
PVM_A32_OP_UMAAL,
PVM_A32_OP_UMLAL,
PVM_A32_OP_UMULL,
PVM_A32_OP_SMLALXY,
PVM_A32_OP_SMLAXY,
PVM_A32_OP_SMULXY,
PVM_A32_OP_SMLAWY,
PVM_A32_OP_SMULWY,
PVM_A32_OP_SMMUL,
PVM_A32_OP_SMMLA,
PVM_A32_OP_SMMLS,
PVM_A32_OP_SMUAD,
PVM_A32_OP_SMLAD,
PVM_A32_OP_SMLALD,
PVM_A32_OP_SMUSD,
PVM_A32_OP_SMLSD,
PVM_A32_OP_SMLSLD,
PVM_A32_OP_SADD8,
PVM_A32_OP_SADD16,
PVM_A32_OP_SASX,
PVM_A32_OP_SSAX,
PVM_A32_OP_SSUB8,
PVM_A32_OP_SSUB16,
PVM_A32_OP_UADD8,
PVM_A32_OP_UADD16,
PVM_A32_OP_UASX,
PVM_A32_OP_USAX,
PVM_A32_OP_USUB8,
PVM_A32_OP_USUB16,
PVM_A32_OP_QADD8,
PVM_A32_OP_QADD16,
PVM_A32_OP_QASX,
PVM_A32_OP_QSAX,
PVM_A32_OP_QSUB8,
PVM_A32_OP_QSUB16,
PVM_A32_OP_UQADD8,
PVM_A32_OP_UQADD16,
PVM_A32_OP_UQASX,
PVM_A32_OP_UQSAX,
PVM_A32_OP_UQSUB8,
PVM_A32_OP_UQSUB16,
PVM_A32_OP_SHADD8,
PVM_A32_OP_SHADD16,
PVM_A32_OP_SHASX,
PVM_A32_OP_SHSAX,
PVM_A32_OP_SHSUB8,
PVM_A32_OP_SHSUB16,
PVM_A32_OP_UHADD8,
PVM_A32_OP_UHADD16,
PVM_A32_OP_UHASX,
PVM_A32_OP_UHSAX,
PVM_A32_OP_UHSUB8,
PVM_A32_OP_UHSUB16,
PVM_A32_OP_QADD,
PVM_A32_OP_QSUB,
PVM_A32_OP_QDADD,
PVM_A32_OP_QDSUB,
PVM_A32_OP_MRS,
PVM_A32_OP_MSR_IMM,
PVM_A32_OP_MSR_REG,
PVM_A32_OP_STOP,
} pvm_jit_decoder_arm32_opcode_t;
#endif // POUND_JIT_DECODER_ARM32_OPCODES_H

523
src/jit/frontend/decoder/arm32_table.c → src/jit/frontend/decoder/arm32_table_generated.c
View file

@ -1,269 +1,270 @@
/* GENERATED FILE - DO NOT EDIT */
/* This file is generated by scripts/generate_jit_assets.py */
/* This file is generated by scripts/generate_jit_decoder_a32_table.py */
#include "arm32.h"
#include "arm32_table.h"
#include "arm32_table_generated.h"
static const pvm_jit_decoder_arm32_instruction_info_t g_instructions[259] = {
{ "DMB", "1111010101111111111100000101oooo", PVM_A32_OP_DMB, 0xfffffff0U, 0xf57ff050U },
{ "DSB", "1111010101111111111100000100oooo", PVM_A32_OP_DSB, 0xfffffff0U, 0xf57ff040U },
{ "ISB", "1111010101111111111100000110oooo", PVM_A32_OP_ISB, 0xfffffff0U, 0xf57ff060U },
{ "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_BLX_IMM, 0xfe000000U, 0xfa000000U },
{ "BLX (reg)", "cccc000100101111111111110011mmmm", PVM_A32_OP_BLX_REG, 0x0ffffff0U, 0x012fff30U },
{ "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_B, 0x0f000000U, 0x0a000000U },
{ "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_BL, 0x0f000000U, 0x0b000000U },
{ "BX", "cccc000100101111111111110001mmmm", PVM_A32_OP_BX, 0x0ffffff0U, 0x012fff10U },
{ "BXJ", "cccc000100101111111111110010mmmm", PVM_A32_OP_BXJ, 0x0ffffff0U, 0x012fff20U },
{ "RFE", "1111100--0-1----0000101000000000", PVM_A32_OP_RFE, 0xfe50ffffU, 0xf8100a00U },
{ "SRS", "1111100--1-0110100000101000-----", PVM_A32_OP_SRS, 0xfe5fffe0U, 0xf84d0500U },
{ "CPS", "111100010000---00000000---0-----", PVM_A32_OP_CPS, 0xfff1fe20U, 0xf1000000U },
{ "SETEND", "1111000100000001000000e000000000", PVM_A32_OP_SETEND, 0xfffffdffU, 0xf1010000U },
{ "CRC32", "cccc00010zz0nnnndddd00000100mmmm", PVM_A32_OP_CRC32, 0x0f900ff0U, 0x01000040U },
{ "CRC32C", "cccc00010zz0nnnndddd00100100mmmm", PVM_A32_OP_CRC32C, 0x0f900ff0U, 0x01000240U },
{ "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM", PVM_A32_OP_CDP, 0x0f000010U, 0x0e000000U },
{ "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM", PVM_A32_OP_MCR, 0x0f100010U, 0x0e000010U },
{ "MCRR", "cccc11000100uuuuttttppppooooMMMM", PVM_A32_OP_MCRR, 0x0ff00000U, 0x0c400000U },
{ "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM", PVM_A32_OP_MRC, 0x0f100010U, 0x0e100010U },
{ "MRRC", "cccc11000101uuuuttttppppooooMMMM", PVM_A32_OP_MRRC, 0x0ff00000U, 0x0c500000U },
{ "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv", PVM_A32_OP_LDC, 0x0e100000U, 0x0c100000U },
{ "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv", PVM_A32_OP_STC, 0x0e100000U, 0x0c000000U },
{ "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_ADC_IMM, 0x0fe00000U, 0x02a00000U },
{ "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_ADC_REG, 0x0fe00010U, 0x00a00000U },
{ "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm", PVM_A32_OP_ADC_RSR, 0x0fe00090U, 0x00a00010U },
{ "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_ADD_IMM, 0x0fe00000U, 0x02800000U },
{ "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_ADD_REG, 0x0fe00010U, 0x00800000U },
{ "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm", PVM_A32_OP_ADD_RSR, 0x0fe00090U, 0x00800010U },
{ "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_AND_IMM, 0x0fe00000U, 0x02000000U },
{ "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_AND_REG, 0x0fe00010U, 0x00000000U },
{ "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm", PVM_A32_OP_AND_RSR, 0x0fe00090U, 0x00000010U },
{ "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_BIC_IMM, 0x0fe00000U, 0x03c00000U },
{ "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_BIC_REG, 0x0fe00010U, 0x01c00000U },
{ "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm", PVM_A32_OP_BIC_RSR, 0x0fe00090U, 0x01c00010U },
{ "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv", PVM_A32_OP_CMN_IMM, 0x0ff0f000U, 0x03700000U },
{ "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm", PVM_A32_OP_CMN_REG, 0x0ff0f010U, 0x01700000U },
{ "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm", PVM_A32_OP_CMN_RSR, 0x0ff0f090U, 0x01700010U },
{ "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv", PVM_A32_OP_CMP_IMM, 0x0ff0f000U, 0x03500000U },
{ "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm", PVM_A32_OP_CMP_REG, 0x0ff0f010U, 0x01500000U },
{ "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm", PVM_A32_OP_CMP_RSR, 0x0ff0f090U, 0x01500010U },
{ "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_EOR_IMM, 0x0fe00000U, 0x02200000U },
{ "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_EOR_REG, 0x0fe00010U, 0x00200000U },
{ "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm", PVM_A32_OP_EOR_RSR, 0x0fe00090U, 0x00200010U },
{ "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv", PVM_A32_OP_MOV_IMM, 0x0fef0000U, 0x03a00000U },
{ "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm", PVM_A32_OP_MOV_REG, 0x0fef0010U, 0x01a00000U },
{ "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm", PVM_A32_OP_MOV_RSR, 0x0fef0090U, 0x01a00010U },
{ "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv", PVM_A32_OP_MVN_IMM, 0x0fef0000U, 0x03e00000U },
{ "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm", PVM_A32_OP_MVN_REG, 0x0fef0010U, 0x01e00000U },
{ "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm", PVM_A32_OP_MVN_RSR, 0x0fef0090U, 0x01e00010U },
{ "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_ORR_IMM, 0x0fe00000U, 0x03800000U },
{ "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_ORR_REG, 0x0fe00010U, 0x01800000U },
{ "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm", PVM_A32_OP_ORR_RSR, 0x0fe00090U, 0x01800010U },
{ "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_RSB_IMM, 0x0fe00000U, 0x02600000U },
{ "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_RSB_REG, 0x0fe00010U, 0x00600000U },
{ "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm", PVM_A32_OP_RSB_RSR, 0x0fe00090U, 0x00600010U },
{ "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_RSC_IMM, 0x0fe00000U, 0x02e00000U },
{ "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_RSC_REG, 0x0fe00010U, 0x00e00000U },
{ "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm", PVM_A32_OP_RSC_RSR, 0x0fe00090U, 0x00e00010U },
{ "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_SBC_IMM, 0x0fe00000U, 0x02c00000U },
{ "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_SBC_REG, 0x0fe00010U, 0x00c00000U },
{ "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm", PVM_A32_OP_SBC_RSR, 0x0fe00090U, 0x00c00010U },
{ "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv", PVM_A32_OP_SUB_IMM, 0x0fe00000U, 0x02400000U },
{ "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm", PVM_A32_OP_SUB_REG, 0x0fe00010U, 0x00400000U },
{ "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm", PVM_A32_OP_SUB_RSR, 0x0fe00090U, 0x00400010U },
{ "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv", PVM_A32_OP_TEQ_IMM, 0x0ff0f000U, 0x03300000U },
{ "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm", PVM_A32_OP_TEQ_REG, 0x0ff0f010U, 0x01300000U },
{ "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm", PVM_A32_OP_TEQ_RSR, 0x0ff0f090U, 0x01300010U },
{ "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv", PVM_A32_OP_TST_IMM, 0x0ff0f000U, 0x03100000U },
{ "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm", PVM_A32_OP_TST_REG, 0x0ff0f010U, 0x01100000U },
{ "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm", PVM_A32_OP_TST_RSR, 0x0ff0f090U, 0x01100010U },
{ "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv", PVM_A32_OP_BKPT, 0x0ff000f0U, 0x01200070U },
{ "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv", PVM_A32_OP_SVC, 0x0f000000U, 0x0f000000U },
{ "UDF", "111001111111------------1111----", PVM_A32_OP_UDF, 0xfff000f0U, 0xe7f000f0U },
{ "SXTB", "cccc011010101111ddddrr000111mmmm", PVM_A32_OP_SXTB, 0x0fff03f0U, 0x06af0070U },
{ "SXTB16", "cccc011010001111ddddrr000111mmmm", PVM_A32_OP_SXTB16, 0x0fff03f0U, 0x068f0070U },
{ "SXTH", "cccc011010111111ddddrr000111mmmm", PVM_A32_OP_SXTH, 0x0fff03f0U, 0x06bf0070U },
{ "SXTAB", "cccc01101010nnnnddddrr000111mmmm", PVM_A32_OP_SXTAB, 0x0ff003f0U, 0x06a00070U },
{ "SXTAB16", "cccc01101000nnnnddddrr000111mmmm", PVM_A32_OP_SXTAB16, 0x0ff003f0U, 0x06800070U },
{ "SXTAH", "cccc01101011nnnnddddrr000111mmmm", PVM_A32_OP_SXTAH, 0x0ff003f0U, 0x06b00070U },
{ "UXTB", "cccc011011101111ddddrr000111mmmm", PVM_A32_OP_UXTB, 0x0fff03f0U, 0x06ef0070U },
{ "UXTB16", "cccc011011001111ddddrr000111mmmm", PVM_A32_OP_UXTB16, 0x0fff03f0U, 0x06cf0070U },
{ "UXTH", "cccc011011111111ddddrr000111mmmm", PVM_A32_OP_UXTH, 0x0fff03f0U, 0x06ff0070U },
{ "UXTAB", "cccc01101110nnnnddddrr000111mmmm", PVM_A32_OP_UXTAB, 0x0ff003f0U, 0x06e00070U },
{ "UXTAB16", "cccc01101100nnnnddddrr000111mmmm", PVM_A32_OP_UXTAB16, 0x0ff003f0U, 0x06c00070U },
{ "UXTAH", "cccc01101111nnnnddddrr000111mmmm", PVM_A32_OP_UXTAH, 0x0ff003f0U, 0x06f00070U },
{ "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii", PVM_A32_OP_PLD_IMM, 0xff30f000U, 0xf510f000U },
{ "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm", PVM_A32_OP_PLD_REG, 0xff30f010U, 0xf710f000U },
{ "SEV", "----0011001000001111000000000100", PVM_A32_OP_SEV, 0x0fffffffU, 0x0320f004U },
{ "SEVL", "----0011001000001111000000000101", PVM_A32_OP_SEVL, 0x0fffffffU, 0x0320f005U },
{ "WFE", "----0011001000001111000000000010", PVM_A32_OP_WFE, 0x0fffffffU, 0x0320f002U },
{ "WFI", "----0011001000001111000000000011", PVM_A32_OP_WFI, 0x0fffffffU, 0x0320f003U },
{ "YIELD", "----0011001000001111000000000001", PVM_A32_OP_YIELD, 0x0fffffffU, 0x0320f001U },
{ "NOP", "----0011001000001111000000000000", PVM_A32_OP_NOP, 0x0fffffffU, 0x0320f000U },
{ "CLREX", "11110101011111111111000000011111", PVM_A32_OP_CLREX, 0xffffffffU, 0xf57ff01fU },
{ "SWP", "cccc00010000nnnntttt00001001uuuu", PVM_A32_OP_SWP, 0x0ff00ff0U, 0x01000090U },
{ "SWPB", "cccc00010100nnnntttt00001001uuuu", PVM_A32_OP_SWPB, 0x0ff00ff0U, 0x01400090U },
{ "STL", "cccc00011000nnnn111111001001tttt", PVM_A32_OP_STL, 0x0ff0fff0U, 0x0180fc90U },
{ "STLEX", "cccc00011000nnnndddd11101001tttt", PVM_A32_OP_STLEX, 0x0ff00ff0U, 0x01800e90U },
{ "STREX", "cccc00011000nnnndddd11111001mmmm", PVM_A32_OP_STREX, 0x0ff00ff0U, 0x01800f90U },
{ "LDA", "cccc00011001nnnndddd110010011111", PVM_A32_OP_LDA, 0x0ff00fffU, 0x01900c9fU },
{ "LDAEX", "cccc00011001nnnndddd111010011111", PVM_A32_OP_LDAEX, 0x0ff00fffU, 0x01900e9fU },
{ "LDREX", "cccc00011001nnnndddd111110011111", PVM_A32_OP_LDREX, 0x0ff00fffU, 0x01900f9fU },
{ "STLEXD", "cccc00011010nnnndddd11101001mmmm", PVM_A32_OP_STLEXD, 0x0ff00ff0U, 0x01a00e90U },
{ "STREXD", "cccc00011010nnnndddd11111001mmmm", PVM_A32_OP_STREXD, 0x0ff00ff0U, 0x01a00f90U },
{ "LDAEXD", "cccc00011011nnnndddd111010011111", PVM_A32_OP_LDAEXD, 0x0ff00fffU, 0x01b00e9fU },
{ "LDREXD", "cccc00011011nnnndddd111110011111", PVM_A32_OP_LDREXD, 0x0ff00fffU, 0x01b00f9fU },
{ "STLB", "cccc00011100nnnn111111001001tttt", PVM_A32_OP_STLB, 0x0ff0fff0U, 0x01c0fc90U },
{ "STLEXB", "cccc00011100nnnndddd11101001mmmm", PVM_A32_OP_STLEXB, 0x0ff00ff0U, 0x01c00e90U },
{ "STREXB", "cccc00011100nnnndddd11111001mmmm", PVM_A32_OP_STREXB, 0x0ff00ff0U, 0x01c00f90U },
{ "LDAB", "cccc00011101nnnndddd110010011111", PVM_A32_OP_LDAB, 0x0ff00fffU, 0x01d00c9fU },
{ "LDAEXB", "cccc00011101nnnndddd111010011111", PVM_A32_OP_LDAEXB, 0x0ff00fffU, 0x01d00e9fU },
{ "LDREXB", "cccc00011101nnnndddd111110011111", PVM_A32_OP_LDREXB, 0x0ff00fffU, 0x01d00f9fU },
{ "STLH", "cccc00011110nnnn111111001001mmmm", PVM_A32_OP_STLH, 0x0ff0fff0U, 0x01e0fc90U },
{ "STLEXH", "cccc00011110nnnndddd11101001mmmm", PVM_A32_OP_STLEXH, 0x0ff00ff0U, 0x01e00e90U },
{ "STREXH", "cccc00011110nnnndddd11111001mmmm", PVM_A32_OP_STREXH, 0x0ff00ff0U, 0x01e00f90U },
{ "LDAH", "cccc00011111nnnndddd110010011111", PVM_A32_OP_LDAH, 0x0ff00fffU, 0x01f00c9fU },
{ "LDAEXH", "cccc00011111nnnndddd111010011111", PVM_A32_OP_LDAEXH, 0x0ff00fffU, 0x01f00e9fU },
{ "LDREXH", "cccc00011111nnnndddd111110011111", PVM_A32_OP_LDREXH, 0x0ff00fffU, 0x01f00f9fU },
{ "LDRBT (A1)", "----0100-111--------------------", PVM_A32_OP_LDRBT, 0x0f700000U, 0x04700000U },
{ "LDRBT (A2)", "----0110-111---------------0----", PVM_A32_OP_LDRBT, 0x0f700010U, 0x06700000U },
{ "LDRHT (A1)", "----0000-111------------1011----", PVM_A32_OP_LDRHT, 0x0f7000f0U, 0x007000b0U },
{ "LDRHT (A1)", "----0000-1111111--------1011----", PVM_A32_OP_LDRHT, 0x0f7f00f0U, 0x007f00b0U },
{ "LDRHT (A2)", "----0000-011--------00001011----", PVM_A32_OP_LDRHT, 0x0f700ff0U, 0x003000b0U },
{ "LDRSBT (A1)", "----0000-111------------1101----", PVM_A32_OP_LDRSBT, 0x0f7000f0U, 0x007000d0U },
{ "LDRSBT (A2)", "----0000-011--------00001101----", PVM_A32_OP_LDRSBT, 0x0f700ff0U, 0x003000d0U },
{ "LDRSHT (A1)", "----0000-111------------1111----", PVM_A32_OP_LDRSHT, 0x0f7000f0U, 0x007000f0U },
{ "LDRSHT (A2)", "----0000-011--------00001111----", PVM_A32_OP_LDRSHT, 0x0f700ff0U, 0x003000f0U },
{ "LDRT (A1)", "----0100-011--------------------", PVM_A32_OP_LDRT, 0x0f700000U, 0x04300000U },
{ "LDRT (A2)", "----0110-011---------------0----", PVM_A32_OP_LDRT, 0x0f700010U, 0x06300000U },
{ "STRBT (A1)", "----0100-110--------------------", PVM_A32_OP_STRBT, 0x0f700000U, 0x04600000U },
{ "STRBT (A2)", "----0110-110---------------0----", PVM_A32_OP_STRBT, 0x0f700010U, 0x06600000U },
{ "STRHT (A1)", "----0000-110------------1011----", PVM_A32_OP_STRHT, 0x0f7000f0U, 0x006000b0U },
{ "STRHT (A2)", "----0000-010--------00001011----", PVM_A32_OP_STRHT, 0x0f700ff0U, 0x002000b0U },
{ "STRT (A1)", "----0100-010--------------------", PVM_A32_OP_STRT, 0x0f700000U, 0x04200000U },
{ "STRT (A2)", "----0110-010---------------0----", PVM_A32_OP_STRT, 0x0f700010U, 0x06200000U },
{ "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv", PVM_A32_OP_LDR_LIT, 0x0f7f0000U, 0x051f0000U },
{ "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv", PVM_A32_OP_LDR_IMM, 0x0e500000U, 0x04100000U },
{ "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm", PVM_A32_OP_LDR_REG, 0x0e500010U, 0x06100000U },
{ "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv", PVM_A32_OP_LDRB_LIT, 0x0f7f0000U, 0x055f0000U },
{ "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv", PVM_A32_OP_LDRB_IMM, 0x0e500000U, 0x04500000U },
{ "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm", PVM_A32_OP_LDRB_REG, 0x0e500010U, 0x06500000U },
{ "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv", PVM_A32_OP_LDRD_LIT, 0x0f7f00f0U, 0x014f00d0U },
{ "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv", PVM_A32_OP_LDRD_IMM, 0x0e5000f0U, 0x004000d0U },
{ "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm", PVM_A32_OP_LDRD_REG, 0x0e500ff0U, 0x000000d0U },
{ "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv", PVM_A32_OP_LDRH_LIT, 0x0e5f00f0U, 0x005f00b0U },
{ "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv", PVM_A32_OP_LDRH_IMM, 0x0e5000f0U, 0x005000b0U },
{ "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm", PVM_A32_OP_LDRH_REG, 0x0e500ff0U, 0x001000b0U },
{ "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv", PVM_A32_OP_LDRSB_LIT, 0x0f7f00f0U, 0x015f00d0U },
{ "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv", PVM_A32_OP_LDRSB_IMM, 0x0e5000f0U, 0x005000d0U },
{ "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm", PVM_A32_OP_LDRSB_REG, 0x0e500ff0U, 0x001000d0U },
{ "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv", PVM_A32_OP_LDRSH_LIT, 0x0f7f00f0U, 0x015f00f0U },
{ "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv", PVM_A32_OP_LDRSH_IMM, 0x0e5000f0U, 0x005000f0U },
{ "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm", PVM_A32_OP_LDRSH_REG, 0x0e500ff0U, 0x001000f0U },
{ "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv", PVM_A32_OP_STR_IMM, 0x0e500000U, 0x04000000U },
{ "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm", PVM_A32_OP_STR_REG, 0x0e500010U, 0x06000000U },
{ "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv", PVM_A32_OP_STRB_IMM, 0x0e500000U, 0x04400000U },
{ "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm", PVM_A32_OP_STRB_REG, 0x0e500010U, 0x06400000U },
{ "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv", PVM_A32_OP_STRD_IMM, 0x0e5000f0U, 0x004000f0U },
{ "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm", PVM_A32_OP_STRD_REG, 0x0e500ff0U, 0x000000f0U },
{ "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv", PVM_A32_OP_STRH_IMM, 0x0e5000f0U, 0x004000b0U },
{ "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm", PVM_A32_OP_STRH_REG, 0x0e500ff0U, 0x000000b0U },
{ "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDM, 0x0fd00000U, 0x08900000U },
{ "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDMDA, 0x0fd00000U, 0x08100000U },
{ "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDMDB, 0x0fd00000U, 0x09100000U },
{ "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_LDMIB, 0x0fd00000U, 0x09900000U },
{ "LDM (usr reg)", "----100--101----0---------------", PVM_A32_OP_LDM_USR, 0x0e708000U, 0x08500000U },
{ "LDM (exce ret)", "----100--1-1----1---------------", PVM_A32_OP_LDM_ERET, 0x0e508000U, 0x08508000U },
{ "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STM, 0x0fd00000U, 0x08800000U },
{ "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STMDA, 0x0fd00000U, 0x08000000U },
{ "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STMDB, 0x0fd00000U, 0x09000000U },
{ "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx", PVM_A32_OP_STMIB, 0x0fd00000U, 0x09800000U },
{ "STM (usr reg)", "----100--100--------------------", PVM_A32_OP_STM_USR, 0x0e700000U, 0x08400000U },
{ "BFC", "cccc0111110vvvvvddddvvvvv0011111", PVM_A32_OP_BFC, 0x0fe0007fU, 0x07c0001fU },
{ "BFI", "cccc0111110vvvvvddddvvvvv001nnnn", PVM_A32_OP_BFI, 0x0fe00070U, 0x07c00010U },
{ "CLZ", "cccc000101101111dddd11110001mmmm", PVM_A32_OP_CLZ, 0x0fff0ff0U, 0x016f0f10U },
{ "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv", PVM_A32_OP_MOVT, 0x0ff00000U, 0x03400000U },
{ "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv", PVM_A32_OP_MOVW, 0x0ff00000U, 0x03000000U },
{ "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn", PVM_A32_OP_SBFX, 0x0fe00070U, 0x07a00050U },
{ "SEL", "cccc01101000nnnndddd11111011mmmm", PVM_A32_OP_SEL, 0x0ff00ff0U, 0x06800fb0U },
{ "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn", PVM_A32_OP_UBFX, 0x0fe00070U, 0x07e00050U },
{ "USAD8", "cccc01111000dddd1111mmmm0001nnnn", PVM_A32_OP_USAD8, 0x0ff0f0f0U, 0x0780f010U },
{ "USADA8", "cccc01111000ddddaaaammmm0001nnnn", PVM_A32_OP_USADA8, 0x0ff000f0U, 0x07800010U },
{ "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm", PVM_A32_OP_PKHBT, 0x0ff00070U, 0x06800010U },
{ "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm", PVM_A32_OP_PKHTB, 0x0ff00070U, 0x06800050U },
{ "RBIT", "cccc011011111111dddd11110011mmmm", PVM_A32_OP_RBIT, 0x0fff0ff0U, 0x06ff0f30U },
{ "REV", "cccc011010111111dddd11110011mmmm", PVM_A32_OP_REV, 0x0fff0ff0U, 0x06bf0f30U },
{ "REV16", "cccc011010111111dddd11111011mmmm", PVM_A32_OP_REV16, 0x0fff0ff0U, 0x06bf0fb0U },
{ "REVSH", "cccc011011111111dddd11111011mmmm", PVM_A32_OP_REVSH, 0x0fff0ff0U, 0x06ff0fb0U },
{ "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn", PVM_A32_OP_SSAT, 0x0fe00030U, 0x06a00010U },
{ "SSAT16", "cccc01101010vvvvdddd11110011nnnn", PVM_A32_OP_SSAT16, 0x0ff00ff0U, 0x06a00f30U },
{ "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn", PVM_A32_OP_USAT, 0x0fe00030U, 0x06e00010U },
{ "USAT16", "cccc01101110vvvvdddd11110011nnnn", PVM_A32_OP_USAT16, 0x0ff00ff0U, 0x06e00f30U },
{ "SDIV", "cccc01110001dddd1111mmmm0001nnnn", PVM_A32_OP_SDIV, 0x0ff0f0f0U, 0x0710f010U },
{ "UDIV", "cccc01110011dddd1111mmmm0001nnnn", PVM_A32_OP_UDIV, 0x0ff0f0f0U, 0x0730f010U },
{ "MLA", "cccc0000001Sddddaaaammmm1001nnnn", PVM_A32_OP_MLA, 0x0fe000f0U, 0x00200090U },
{ "MLS", "cccc00000110ddddaaaammmm1001nnnn", PVM_A32_OP_MLS, 0x0ff000f0U, 0x00600090U },
{ "MUL", "cccc0000000Sdddd0000mmmm1001nnnn", PVM_A32_OP_MUL, 0x0fe0f0f0U, 0x00000090U },
{ "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn", PVM_A32_OP_SMLAL, 0x0fe000f0U, 0x00e00090U },
{ "SMULL", "cccc0000110Sddddaaaammmm1001nnnn", PVM_A32_OP_SMULL, 0x0fe000f0U, 0x00c00090U },
{ "UMAAL", "cccc00000100ddddaaaammmm1001nnnn", PVM_A32_OP_UMAAL, 0x0ff000f0U, 0x00400090U },
{ "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn", PVM_A32_OP_UMLAL, 0x0fe000f0U, 0x00a00090U },
{ "UMULL", "cccc0000100Sddddaaaammmm1001nnnn", PVM_A32_OP_UMULL, 0x0fe000f0U, 0x00800090U },
{ "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn", PVM_A32_OP_SMLALXY, 0x0ff00090U, 0x01400080U },
{ "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn", PVM_A32_OP_SMLAXY, 0x0ff00090U, 0x01000080U },
{ "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn", PVM_A32_OP_SMULXY, 0x0ff0f090U, 0x01600080U },
{ "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn", PVM_A32_OP_SMLAWY, 0x0ff000b0U, 0x01200080U },
{ "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn", PVM_A32_OP_SMULWY, 0x0ff0f0b0U, 0x012000a0U },
{ "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn", PVM_A32_OP_SMMUL, 0x0ff0f0d0U, 0x0750f010U },
{ "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn", PVM_A32_OP_SMMLA, 0x0ff000d0U, 0x07500010U },
{ "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn", PVM_A32_OP_SMMLS, 0x0ff000d0U, 0x075000d0U },
{ "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn", PVM_A32_OP_SMUAD, 0x0ff0f0d0U, 0x0700f010U },
{ "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn", PVM_A32_OP_SMLAD, 0x0ff000d0U, 0x07000010U },
{ "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn", PVM_A32_OP_SMLALD, 0x0ff000d0U, 0x07400010U },
{ "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn", PVM_A32_OP_SMUSD, 0x0ff0f0d0U, 0x0700f050U },
{ "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn", PVM_A32_OP_SMLSD, 0x0ff000d0U, 0x07000050U },
{ "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn", PVM_A32_OP_SMLSLD, 0x0ff000d0U, 0x07400050U },
{ "SADD8", "cccc01100001nnnndddd11111001mmmm", PVM_A32_OP_SADD8, 0x0ff00ff0U, 0x06100f90U },
{ "SADD16", "cccc01100001nnnndddd11110001mmmm", PVM_A32_OP_SADD16, 0x0ff00ff0U, 0x06100f10U },
{ "SASX", "cccc01100001nnnndddd11110011mmmm", PVM_A32_OP_SASX, 0x0ff00ff0U, 0x06100f30U },
{ "SSAX", "cccc01100001nnnndddd11110101mmmm", PVM_A32_OP_SSAX, 0x0ff00ff0U, 0x06100f50U },
{ "SSUB8", "cccc01100001nnnndddd11111111mmmm", PVM_A32_OP_SSUB8, 0x0ff00ff0U, 0x06100ff0U },
{ "SSUB16", "cccc01100001nnnndddd11110111mmmm", PVM_A32_OP_SSUB16, 0x0ff00ff0U, 0x06100f70U },
{ "UADD8", "cccc01100101nnnndddd11111001mmmm", PVM_A32_OP_UADD8, 0x0ff00ff0U, 0x06500f90U },
{ "UADD16", "cccc01100101nnnndddd11110001mmmm", PVM_A32_OP_UADD16, 0x0ff00ff0U, 0x06500f10U },
{ "UASX", "cccc01100101nnnndddd11110011mmmm", PVM_A32_OP_UASX, 0x0ff00ff0U, 0x06500f30U },
{ "USAX", "cccc01100101nnnndddd11110101mmmm", PVM_A32_OP_USAX, 0x0ff00ff0U, 0x06500f50U },
{ "USUB8", "cccc01100101nnnndddd11111111mmmm", PVM_A32_OP_USUB8, 0x0ff00ff0U, 0x06500ff0U },
{ "USUB16", "cccc01100101nnnndddd11110111mmmm", PVM_A32_OP_USUB16, 0x0ff00ff0U, 0x06500f70U },
{ "QADD8", "cccc01100010nnnndddd11111001mmmm", PVM_A32_OP_QADD8, 0x0ff00ff0U, 0x06200f90U },
{ "QADD16", "cccc01100010nnnndddd11110001mmmm", PVM_A32_OP_QADD16, 0x0ff00ff0U, 0x06200f10U },
{ "QASX", "cccc01100010nnnndddd11110011mmmm", PVM_A32_OP_QASX, 0x0ff00ff0U, 0x06200f30U },
{ "QSAX", "cccc01100010nnnndddd11110101mmmm", PVM_A32_OP_QSAX, 0x0ff00ff0U, 0x06200f50U },
{ "QSUB8", "cccc01100010nnnndddd11111111mmmm", PVM_A32_OP_QSUB8, 0x0ff00ff0U, 0x06200ff0U },
{ "QSUB16", "cccc01100010nnnndddd11110111mmmm", PVM_A32_OP_QSUB16, 0x0ff00ff0U, 0x06200f70U },
{ "UQADD8", "cccc01100110nnnndddd11111001mmmm", PVM_A32_OP_UQADD8, 0x0ff00ff0U, 0x06600f90U },
{ "UQADD16", "cccc01100110nnnndddd11110001mmmm", PVM_A32_OP_UQADD16, 0x0ff00ff0U, 0x06600f10U },
{ "UQASX", "cccc01100110nnnndddd11110011mmmm", PVM_A32_OP_UQASX, 0x0ff00ff0U, 0x06600f30U },
{ "UQSAX", "cccc01100110nnnndddd11110101mmmm", PVM_A32_OP_UQSAX, 0x0ff00ff0U, 0x06600f50U },
{ "UQSUB8", "cccc01100110nnnndddd11111111mmmm", PVM_A32_OP_UQSUB8, 0x0ff00ff0U, 0x06600ff0U },
{ "UQSUB16", "cccc01100110nnnndddd11110111mmmm", PVM_A32_OP_UQSUB16, 0x0ff00ff0U, 0x06600f70U },
{ "SHADD8", "cccc01100011nnnndddd11111001mmmm", PVM_A32_OP_SHADD8, 0x0ff00ff0U, 0x06300f90U },
{ "SHADD16", "cccc01100011nnnndddd11110001mmmm", PVM_A32_OP_SHADD16, 0x0ff00ff0U, 0x06300f10U },
{ "SHASX", "cccc01100011nnnndddd11110011mmmm", PVM_A32_OP_SHASX, 0x0ff00ff0U, 0x06300f30U },
{ "SHSAX", "cccc01100011nnnndddd11110101mmmm", PVM_A32_OP_SHSAX, 0x0ff00ff0U, 0x06300f50U },
{ "SHSUB8", "cccc01100011nnnndddd11111111mmmm", PVM_A32_OP_SHSUB8, 0x0ff00ff0U, 0x06300ff0U },
{ "SHSUB16", "cccc01100011nnnndddd11110111mmmm", PVM_A32_OP_SHSUB16, 0x0ff00ff0U, 0x06300f70U },
{ "UHADD8", "cccc01100111nnnndddd11111001mmmm", PVM_A32_OP_UHADD8, 0x0ff00ff0U, 0x06700f90U },
{ "UHADD16", "cccc01100111nnnndddd11110001mmmm", PVM_A32_OP_UHADD16, 0x0ff00ff0U, 0x06700f10U },
{ "UHASX", "cccc01100111nnnndddd11110011mmmm", PVM_A32_OP_UHASX, 0x0ff00ff0U, 0x06700f30U },
{ "UHSAX", "cccc01100111nnnndddd11110101mmmm", PVM_A32_OP_UHSAX, 0x0ff00ff0U, 0x06700f50U },
{ "UHSUB8", "cccc01100111nnnndddd11111111mmmm", PVM_A32_OP_UHSUB8, 0x0ff00ff0U, 0x06700ff0U },
{ "UHSUB16", "cccc01100111nnnndddd11110111mmmm", PVM_A32_OP_UHSUB16, 0x0ff00ff0U, 0x06700f70U },
{ "QADD", "cccc00010000nnnndddd00000101mmmm", PVM_A32_OP_QADD, 0x0ff00ff0U, 0x01000050U },
{ "QSUB", "cccc00010010nnnndddd00000101mmmm", PVM_A32_OP_QSUB, 0x0ff00ff0U, 0x01200050U },
{ "QDADD", "cccc00010100nnnndddd00000101mmmm", PVM_A32_OP_QDADD, 0x0ff00ff0U, 0x01400050U },
{ "QDSUB", "cccc00010110nnnndddd00000101mmmm", PVM_A32_OP_QDSUB, 0x0ff00ff0U, 0x01600050U },
{ "MRS", "cccc000100001111dddd000000000000", PVM_A32_OP_MRS, 0x0fff0fffU, 0x010f0000U },
{ "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv", PVM_A32_OP_MSR_IMM, 0x0ff0f000U, 0x0320f000U },
{ "MSR (reg)", "cccc00010010mmmm111100000000nnnn", PVM_A32_OP_MSR_REG, 0x0ff0fff0U, 0x0120f000U },
{ "DMB", "1111010101111111111100000101oooo", 0xfffffff0U, 0xf57ff050U },
{ "DSB", "1111010101111111111100000100oooo", 0xfffffff0U, 0xf57ff040U },
{ "ISB", "1111010101111111111100000110oooo", 0xfffffff0U, 0xf57ff060U },
{ "BLX (imm)", "1111101hvvvvvvvvvvvvvvvvvvvvvvvv", 0xfe000000U, 0xfa000000U },
{ "BLX (reg)", "cccc000100101111111111110011mmmm", 0x0ffffff0U, 0x012fff30U },
{ "B", "cccc1010vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0a000000U },
{ "BL", "cccc1011vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0b000000U },
{ "BX", "cccc000100101111111111110001mmmm", 0x0ffffff0U, 0x012fff10U },
{ "BXJ", "cccc000100101111111111110010mmmm", 0x0ffffff0U, 0x012fff20U },
{ "RFE", "1111100--0-1----0000101000000000", 0xfe50ffffU, 0xf8100a00U },
{ "SRS", "1111100--1-0110100000101000-----", 0xfe5fffe0U, 0xf84d0500U },
{ "CPS", "111100010000---00000000---0-----", 0xfff1fe20U, 0xf1000000U },
{ "SETEND", "1111000100000001000000e000000000", 0xfffffdffU, 0xf1010000U },
{ "CRC32", "cccc00010zz0nnnndddd00000100mmmm", 0x0f900ff0U, 0x01000040U },
{ "CRC32C", "cccc00010zz0nnnndddd00100100mmmm", 0x0f900ff0U, 0x01000240U },
{ "CDP", "cccc1110ooooNNNNDDDDppppooo0MMMM", 0x0f000010U, 0x0e000000U },
{ "MCR", "cccc1110ooo0NNNNttttppppooo1MMMM", 0x0f100010U, 0x0e000010U },
{ "MCRR", "cccc11000100uuuuttttppppooooMMMM", 0x0ff00000U, 0x0c400000U },
{ "MRC", "cccc1110ooo1NNNNttttppppooo1MMMM", 0x0f100010U, 0x0e100010U },
{ "MRRC", "cccc11000101uuuuttttppppooooMMMM", 0x0ff00000U, 0x0c500000U },
{ "LDC", "cccc110pudw1nnnnDDDDppppvvvvvvvv", 0x0e100000U, 0x0c100000U },
{ "STC", "cccc110pudw0nnnnDDDDppppvvvvvvvv", 0x0e100000U, 0x0c000000U },
{ "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02a00000U },
{ "ADC (reg)", "cccc0000101Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00a00000U },
{ "ADC (rsr)", "cccc0000101Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00a00010U },
{ "ADD (imm)", "cccc0010100Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02800000U },
{ "ADD (reg)", "cccc0000100Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00800000U },
{ "ADD (rsr)", "cccc0000100Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00800010U },
{ "AND (imm)", "cccc0010000Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02000000U },
{ "AND (reg)", "cccc0000000Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00000000U },
{ "AND (rsr)", "cccc0000000Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00000010U },
{ "BIC (imm)", "cccc0011110Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x03c00000U },
{ "BIC (reg)", "cccc0001110Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x01c00000U },
{ "BIC (rsr)", "cccc0001110Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x01c00010U },
{ "CMN (imm)", "cccc00110111nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03700000U },
{ "CMN (reg)", "cccc00010111nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01700000U },
{ "CMN (rsr)", "cccc00010111nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01700010U },
{ "CMP (imm)", "cccc00110101nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03500000U },
{ "CMP (reg)", "cccc00010101nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01500000U },
{ "CMP (rsr)", "cccc00010101nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01500010U },
{ "EOR (imm)", "cccc0010001Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02200000U },
{ "EOR (reg)", "cccc0000001Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00200000U },
{ "EOR (rsr)", "cccc0000001Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00200010U },
{ "MOV (imm)", "cccc0011101S0000ddddrrrrvvvvvvvv", 0x0fef0000U, 0x03a00000U },
{ "MOV (reg)", "cccc0001101S0000ddddvvvvvrr0mmmm", 0x0fef0010U, 0x01a00000U },
{ "MOV (rsr)", "cccc0001101S0000ddddssss0rr1mmmm", 0x0fef0090U, 0x01a00010U },
{ "MVN (imm)", "cccc0011111S0000ddddrrrrvvvvvvvv", 0x0fef0000U, 0x03e00000U },
{ "MVN (reg)", "cccc0001111S0000ddddvvvvvrr0mmmm", 0x0fef0010U, 0x01e00000U },
{ "MVN (rsr)", "cccc0001111S0000ddddssss0rr1mmmm", 0x0fef0090U, 0x01e00010U },
{ "ORR (imm)", "cccc0011100Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x03800000U },
{ "ORR (reg)", "cccc0001100Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x01800000U },
{ "ORR (rsr)", "cccc0001100Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x01800010U },
{ "RSB (imm)", "cccc0010011Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02600000U },
{ "RSB (reg)", "cccc0000011Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00600000U },
{ "RSB (rsr)", "cccc0000011Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00600010U },
{ "RSC (imm)", "cccc0010111Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02e00000U },
{ "RSC (reg)", "cccc0000111Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00e00000U },
{ "RSC (rsr)", "cccc0000111Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00e00010U },
{ "SBC (imm)", "cccc0010110Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02c00000U },
{ "SBC (reg)", "cccc0000110Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00c00000U },
{ "SBC (rsr)", "cccc0000110Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00c00010U },
{ "SUB (imm)", "cccc0010010Snnnnddddrrrrvvvvvvvv", 0x0fe00000U, 0x02400000U },
{ "SUB (reg)", "cccc0000010Snnnnddddvvvvvrr0mmmm", 0x0fe00010U, 0x00400000U },
{ "SUB (rsr)", "cccc0000010Snnnnddddssss0rr1mmmm", 0x0fe00090U, 0x00400010U },
{ "TEQ (imm)", "cccc00110011nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03300000U },
{ "TEQ (reg)", "cccc00010011nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01300000U },
{ "TEQ (rsr)", "cccc00010011nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01300010U },
{ "TST (imm)", "cccc00110001nnnn0000rrrrvvvvvvvv", 0x0ff0f000U, 0x03100000U },
{ "TST (reg)", "cccc00010001nnnn0000vvvvvrr0mmmm", 0x0ff0f010U, 0x01100000U },
{ "TST (rsr)", "cccc00010001nnnn0000ssss0rr1mmmm", 0x0ff0f090U, 0x01100010U },
{ "BKPT", "cccc00010010vvvvvvvvvvvv0111vvvv", 0x0ff000f0U, 0x01200070U },
{ "SVC", "cccc1111vvvvvvvvvvvvvvvvvvvvvvvv", 0x0f000000U, 0x0f000000U },
{ "UDF", "111001111111------------1111----", 0xfff000f0U, 0xe7f000f0U },
{ "SXTB", "cccc011010101111ddddrr000111mmmm", 0x0fff03f0U, 0x06af0070U },
{ "SXTB16", "cccc011010001111ddddrr000111mmmm", 0x0fff03f0U, 0x068f0070U },
{ "SXTH", "cccc011010111111ddddrr000111mmmm", 0x0fff03f0U, 0x06bf0070U },
{ "SXTAB", "cccc01101010nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06a00070U },
{ "SXTAB16", "cccc01101000nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06800070U },
{ "SXTAH", "cccc01101011nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06b00070U },
{ "UXTB", "cccc011011101111ddddrr000111mmmm", 0x0fff03f0U, 0x06ef0070U },
{ "UXTB16", "cccc011011001111ddddrr000111mmmm", 0x0fff03f0U, 0x06cf0070U },
{ "UXTH", "cccc011011111111ddddrr000111mmmm", 0x0fff03f0U, 0x06ff0070U },
{ "UXTAB", "cccc01101110nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06e00070U },
{ "UXTAB16", "cccc01101100nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06c00070U },
{ "UXTAH", "cccc01101111nnnnddddrr000111mmmm", 0x0ff003f0U, 0x06f00070U },
{ "PLD (imm)", "11110101uz01nnnn1111iiiiiiiiiiii", 0xff30f000U, 0xf510f000U },
{ "PLD (reg)", "11110111uz01nnnn1111iiiiitt0mmmm", 0xff30f010U, 0xf710f000U },
{ "SEV", "----0011001000001111000000000100", 0x0fffffffU, 0x0320f004U },
{ "SEVL", "----0011001000001111000000000101", 0x0fffffffU, 0x0320f005U },
{ "WFE", "----0011001000001111000000000010", 0x0fffffffU, 0x0320f002U },
{ "WFI", "----0011001000001111000000000011", 0x0fffffffU, 0x0320f003U },
{ "YIELD", "----0011001000001111000000000001", 0x0fffffffU, 0x0320f001U },
{ "NOP", "----0011001000001111000000000000", 0x0fffffffU, 0x0320f000U },
{ "CLREX", "11110101011111111111000000011111", 0xffffffffU, 0xf57ff01fU },
{ "SWP", "cccc00010000nnnntttt00001001uuuu", 0x0ff00ff0U, 0x01000090U },
{ "SWPB", "cccc00010100nnnntttt00001001uuuu", 0x0ff00ff0U, 0x01400090U },
{ "STL", "cccc00011000nnnn111111001001tttt", 0x0ff0fff0U, 0x0180fc90U },
{ "STLEX", "cccc00011000nnnndddd11101001tttt", 0x0ff00ff0U, 0x01800e90U },
{ "STREX", "cccc00011000nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01800f90U },
{ "LDA", "cccc00011001nnnndddd110010011111", 0x0ff00fffU, 0x01900c9fU },
{ "LDAEX", "cccc00011001nnnndddd111010011111", 0x0ff00fffU, 0x01900e9fU },
{ "LDREX", "cccc00011001nnnndddd111110011111", 0x0ff00fffU, 0x01900f9fU },
{ "STLEXD", "cccc00011010nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01a00e90U },
{ "STREXD", "cccc00011010nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01a00f90U },
{ "LDAEXD", "cccc00011011nnnndddd111010011111", 0x0ff00fffU, 0x01b00e9fU },
{ "LDREXD", "cccc00011011nnnndddd111110011111", 0x0ff00fffU, 0x01b00f9fU },
{ "STLB", "cccc00011100nnnn111111001001tttt", 0x0ff0fff0U, 0x01c0fc90U },
{ "STLEXB", "cccc00011100nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01c00e90U },
{ "STREXB", "cccc00011100nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01c00f90U },
{ "LDAB", "cccc00011101nnnndddd110010011111", 0x0ff00fffU, 0x01d00c9fU },
{ "LDAEXB", "cccc00011101nnnndddd111010011111", 0x0ff00fffU, 0x01d00e9fU },
{ "LDREXB", "cccc00011101nnnndddd111110011111", 0x0ff00fffU, 0x01d00f9fU },
{ "STLH", "cccc00011110nnnn111111001001mmmm", 0x0ff0fff0U, 0x01e0fc90U },
{ "STLEXH", "cccc00011110nnnndddd11101001mmmm", 0x0ff00ff0U, 0x01e00e90U },
{ "STREXH", "cccc00011110nnnndddd11111001mmmm", 0x0ff00ff0U, 0x01e00f90U },
{ "LDAH", "cccc00011111nnnndddd110010011111", 0x0ff00fffU, 0x01f00c9fU },
{ "LDAEXH", "cccc00011111nnnndddd111010011111", 0x0ff00fffU, 0x01f00e9fU },
{ "LDREXH", "cccc00011111nnnndddd111110011111", 0x0ff00fffU, 0x01f00f9fU },
{ "LDRBT (A1)", "----0100-111--------------------", 0x0f700000U, 0x04700000U },
{ "LDRBT (A2)", "----0110-111---------------0----", 0x0f700010U, 0x06700000U },
{ "LDRHT (A1)", "----0000-111------------1011----", 0x0f7000f0U, 0x007000b0U },
{ "LDRHT (A1)", "----0000-1111111--------1011----", 0x0f7f00f0U, 0x007f00b0U },
{ "LDRHT (A2)", "----0000-011--------00001011----", 0x0f700ff0U, 0x003000b0U },
{ "LDRSBT (A1)", "----0000-111------------1101----", 0x0f7000f0U, 0x007000d0U },
{ "LDRSBT (A2)", "----0000-011--------00001101----", 0x0f700ff0U, 0x003000d0U },
{ "LDRSHT (A1)", "----0000-111------------1111----", 0x0f7000f0U, 0x007000f0U },
{ "LDRSHT (A2)", "----0000-011--------00001111----", 0x0f700ff0U, 0x003000f0U },
{ "LDRT (A1)", "----0100-011--------------------", 0x0f700000U, 0x04300000U },
{ "LDRT (A2)", "----0110-011---------------0----", 0x0f700010U, 0x06300000U },
{ "STRBT (A1)", "----0100-110--------------------", 0x0f700000U, 0x04600000U },
{ "STRBT (A2)", "----0110-110---------------0----", 0x0f700010U, 0x06600000U },
{ "STRHT (A1)", "----0000-110------------1011----", 0x0f7000f0U, 0x006000b0U },
{ "STRHT (A2)", "----0000-010--------00001011----", 0x0f700ff0U, 0x002000b0U },
{ "STRT (A1)", "----0100-010--------------------", 0x0f700000U, 0x04200000U },
{ "STRT (A2)", "----0110-010---------------0----", 0x0f700010U, 0x06200000U },
{ "LDR (lit)", "cccc0101u0011111ttttvvvvvvvvvvvv", 0x0f7f0000U, 0x051f0000U },
{ "LDR (imm)", "cccc010pu0w1nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04100000U },
{ "LDR (reg)", "cccc011pu0w1nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06100000U },
{ "LDRB (lit)", "cccc0101u1011111ttttvvvvvvvvvvvv", 0x0f7f0000U, 0x055f0000U },
{ "LDRB (imm)", "cccc010pu1w1nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04500000U },
{ "LDRB (reg)", "cccc011pu1w1nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06500000U },
{ "LDRD (lit)", "cccc0001u1001111ttttvvvv1101vvvv", 0x0f7f00f0U, 0x014f00d0U },
{ "LDRD (imm)", "cccc000pu1w0nnnnttttvvvv1101vvvv", 0x0e5000f0U, 0x004000d0U },
{ "LDRD (reg)", "cccc000pu0w0nnnntttt00001101mmmm", 0x0e500ff0U, 0x000000d0U },
{ "LDRH (lit)", "cccc000pu1w11111ttttvvvv1011vvvv", 0x0e5f00f0U, 0x005f00b0U },
{ "LDRH (imm)", "cccc000pu1w1nnnnttttvvvv1011vvvv", 0x0e5000f0U, 0x005000b0U },
{ "LDRH (reg)", "cccc000pu0w1nnnntttt00001011mmmm", 0x0e500ff0U, 0x001000b0U },
{ "LDRSB (lit)", "cccc0001u1011111ttttvvvv1101vvvv", 0x0f7f00f0U, 0x015f00d0U },
{ "LDRSB (imm)", "cccc000pu1w1nnnnttttvvvv1101vvvv", 0x0e5000f0U, 0x005000d0U },
{ "LDRSB (reg)", "cccc000pu0w1nnnntttt00001101mmmm", 0x0e500ff0U, 0x001000d0U },
{ "LDRSH (lit)", "cccc0001u1011111ttttvvvv1111vvvv", 0x0f7f00f0U, 0x015f00f0U },
{ "LDRSH (imm)", "cccc000pu1w1nnnnttttvvvv1111vvvv", 0x0e5000f0U, 0x005000f0U },
{ "LDRSH (reg)", "cccc000pu0w1nnnntttt00001111mmmm", 0x0e500ff0U, 0x001000f0U },
{ "STR (imm)", "cccc010pu0w0nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04000000U },
{ "STR (reg)", "cccc011pu0w0nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06000000U },
{ "STRB (imm)", "cccc010pu1w0nnnnttttvvvvvvvvvvvv", 0x0e500000U, 0x04400000U },
{ "STRB (reg)", "cccc011pu1w0nnnnttttvvvvvrr0mmmm", 0x0e500010U, 0x06400000U },
{ "STRD (imm)", "cccc000pu1w0nnnnttttvvvv1111vvvv", 0x0e5000f0U, 0x004000f0U },
{ "STRD (reg)", "cccc000pu0w0nnnntttt00001111mmmm", 0x0e500ff0U, 0x000000f0U },
{ "STRH (imm)", "cccc000pu1w0nnnnttttvvvv1011vvvv", 0x0e5000f0U, 0x004000b0U },
{ "STRH (reg)", "cccc000pu0w0nnnntttt00001011mmmm", 0x0e500ff0U, 0x000000b0U },
{ "LDM", "cccc100010w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08900000U },
{ "LDMDA", "cccc100000w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08100000U },
{ "LDMDB", "cccc100100w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09100000U },
{ "LDMIB", "cccc100110w1nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09900000U },
{ "LDM (usr reg)", "----100--101----0---------------", 0x0e708000U, 0x08500000U },
{ "LDM (exce ret)", "----100--1-1----1---------------", 0x0e508000U, 0x08508000U },
{ "STM", "cccc100010w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08800000U },
{ "STMDA", "cccc100000w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x08000000U },
{ "STMDB", "cccc100100w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09000000U },
{ "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx", 0x0fd00000U, 0x09800000U },
{ "STM (usr reg)", "----100--100--------------------", 0x0e700000U, 0x08400000U },
{ "BFC", "cccc0111110vvvvvddddvvvvv0011111", 0x0fe0007fU, 0x07c0001fU },
{ "BFI", "cccc0111110vvvvvddddvvvvv001nnnn", 0x0fe00070U, 0x07c00010U },
{ "CLZ", "cccc000101101111dddd11110001mmmm", 0x0fff0ff0U, 0x016f0f10U },
{ "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv", 0x0ff00000U, 0x03400000U },
{ "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv", 0x0ff00000U, 0x03000000U },
{ "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn", 0x0fe00070U, 0x07a00050U },
{ "SEL", "cccc01101000nnnndddd11111011mmmm", 0x0ff00ff0U, 0x06800fb0U },
{ "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn", 0x0fe00070U, 0x07e00050U },
{ "USAD8", "cccc01111000dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0780f010U },
{ "USADA8", "cccc01111000ddddaaaammmm0001nnnn", 0x0ff000f0U, 0x07800010U },
{ "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm", 0x0ff00070U, 0x06800010U },
{ "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm", 0x0ff00070U, 0x06800050U },
{ "RBIT", "cccc011011111111dddd11110011mmmm", 0x0fff0ff0U, 0x06ff0f30U },
{ "REV", "cccc011010111111dddd11110011mmmm", 0x0fff0ff0U, 0x06bf0f30U },
{ "REV16", "cccc011010111111dddd11111011mmmm", 0x0fff0ff0U, 0x06bf0fb0U },
{ "REVSH", "cccc011011111111dddd11111011mmmm", 0x0fff0ff0U, 0x06ff0fb0U },
{ "SSAT", "cccc0110101vvvvvddddvvvvvr01nnnn", 0x0fe00030U, 0x06a00010U },
{ "SSAT16", "cccc01101010vvvvdddd11110011nnnn", 0x0ff00ff0U, 0x06a00f30U },
{ "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn", 0x0fe00030U, 0x06e00010U },
{ "USAT16", "cccc01101110vvvvdddd11110011nnnn", 0x0ff00ff0U, 0x06e00f30U },
{ "SDIV", "cccc01110001dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0710f010U },
{ "UDIV", "cccc01110011dddd1111mmmm0001nnnn", 0x0ff0f0f0U, 0x0730f010U },
{ "MLA", "cccc0000001Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00200090U },
{ "MLS", "cccc00000110ddddaaaammmm1001nnnn", 0x0ff000f0U, 0x00600090U },
{ "MUL", "cccc0000000Sdddd0000mmmm1001nnnn", 0x0fe0f0f0U, 0x00000090U },
{ "SMLAL", "cccc0000111Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00e00090U },
{ "SMULL", "cccc0000110Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00c00090U },
{ "UMAAL", "cccc00000100ddddaaaammmm1001nnnn", 0x0ff000f0U, 0x00400090U },
{ "UMLAL", "cccc0000101Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00a00090U },
{ "UMULL", "cccc0000100Sddddaaaammmm1001nnnn", 0x0fe000f0U, 0x00800090U },
{ "SMLALXY", "cccc00010100ddddaaaammmm1xy0nnnn", 0x0ff00090U, 0x01400080U },
{ "SMLAXY", "cccc00010000ddddaaaammmm1xy0nnnn", 0x0ff00090U, 0x01000080U },
{ "SMULXY", "cccc00010110dddd0000mmmm1xy0nnnn", 0x0ff0f090U, 0x01600080U },
{ "SMLAWY", "cccc00010010ddddaaaammmm1y00nnnn", 0x0ff000b0U, 0x01200080U },
{ "SMULWY", "cccc00010010dddd0000mmmm1y10nnnn", 0x0ff0f0b0U, 0x012000a0U },
{ "SMMUL", "cccc01110101dddd1111mmmm00R1nnnn", 0x0ff0f0d0U, 0x0750f010U },
{ "SMMLA", "cccc01110101ddddaaaammmm00R1nnnn", 0x0ff000d0U, 0x07500010U },
{ "SMMLS", "cccc01110101ddddaaaammmm11R1nnnn", 0x0ff000d0U, 0x075000d0U },
{ "SMUAD", "cccc01110000dddd1111mmmm00M1nnnn", 0x0ff0f0d0U, 0x0700f010U },
{ "SMLAD", "cccc01110000ddddaaaammmm00M1nnnn", 0x0ff000d0U, 0x07000010U },
{ "SMLALD", "cccc01110100ddddaaaammmm00M1nnnn", 0x0ff000d0U, 0x07400010U },
{ "SMUSD", "cccc01110000dddd1111mmmm01M1nnnn", 0x0ff0f0d0U, 0x0700f050U },
{ "SMLSD", "cccc01110000ddddaaaammmm01M1nnnn", 0x0ff000d0U, 0x07000050U },
{ "SMLSLD", "cccc01110100ddddaaaammmm01M1nnnn", 0x0ff000d0U, 0x07400050U },
{ "SADD8", "cccc01100001nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06100f90U },
{ "SADD16", "cccc01100001nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06100f10U },
{ "SASX", "cccc01100001nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06100f30U },
{ "SSAX", "cccc01100001nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06100f50U },
{ "SSUB8", "cccc01100001nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06100ff0U },
{ "SSUB16", "cccc01100001nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06100f70U },
{ "UADD8", "cccc01100101nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06500f90U },
{ "UADD16", "cccc01100101nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06500f10U },
{ "UASX", "cccc01100101nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06500f30U },
{ "USAX", "cccc01100101nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06500f50U },
{ "USUB8", "cccc01100101nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06500ff0U },
{ "USUB16", "cccc01100101nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06500f70U },
{ "QADD8", "cccc01100010nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06200f90U },
{ "QADD16", "cccc01100010nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06200f10U },
{ "QASX", "cccc01100010nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06200f30U },
{ "QSAX", "cccc01100010nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06200f50U },
{ "QSUB8", "cccc01100010nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06200ff0U },
{ "QSUB16", "cccc01100010nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06200f70U },
{ "UQADD8", "cccc01100110nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06600f90U },
{ "UQADD16", "cccc01100110nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06600f10U },
{ "UQASX", "cccc01100110nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06600f30U },
{ "UQSAX", "cccc01100110nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06600f50U },
{ "UQSUB8", "cccc01100110nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06600ff0U },
{ "UQSUB16", "cccc01100110nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06600f70U },
{ "SHADD8", "cccc01100011nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06300f90U },
{ "SHADD16", "cccc01100011nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06300f10U },
{ "SHASX", "cccc01100011nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06300f30U },
{ "SHSAX", "cccc01100011nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06300f50U },
{ "SHSUB8", "cccc01100011nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06300ff0U },
{ "SHSUB16", "cccc01100011nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06300f70U },
{ "UHADD8", "cccc01100111nnnndddd11111001mmmm", 0x0ff00ff0U, 0x06700f90U },
{ "UHADD16", "cccc01100111nnnndddd11110001mmmm", 0x0ff00ff0U, 0x06700f10U },
{ "UHASX", "cccc01100111nnnndddd11110011mmmm", 0x0ff00ff0U, 0x06700f30U },
{ "UHSAX", "cccc01100111nnnndddd11110101mmmm", 0x0ff00ff0U, 0x06700f50U },
{ "UHSUB8", "cccc01100111nnnndddd11111111mmmm", 0x0ff00ff0U, 0x06700ff0U },
{ "UHSUB16", "cccc01100111nnnndddd11110111mmmm", 0x0ff00ff0U, 0x06700f70U },
{ "QADD", "cccc00010000nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01000050U },
{ "QSUB", "cccc00010010nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01200050U },
{ "QDADD", "cccc00010100nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01400050U },
{ "QDSUB", "cccc00010110nnnndddd00000101mmmm", 0x0ff00ff0U, 0x01600050U },
{ "MRS", "cccc000100001111dddd000000000000", 0x0fff0fffU, 0x010f0000U },
{ "MSR (imm)", "cccc00110010mmmm1111rrrrvvvvvvvv", 0x0ff0f000U, 0x0320f000U },
{ "MSR (reg)", "cccc00010010mmmm111100000000nnnn", 0x0ff0fff0U, 0x0120f000U },
};
const decode_bucket_t g_decoder_lookup_table[4096] = {
[0x000] = { .instructions = { &g_instructions[29], }, .count = 1U },
[0x001] = { .instructions = { &g_instructions[30], }, .count = 1U },

2
src/jit/frontend/decoder/arm32_table.h → src/jit/frontend/decoder/arm32_table_generated.h
View file

@ -1,5 +1,3 @@
/* GENERATED FILE - DO NOT EDIT */
/* This file is generated by scripts/generate_jit_assets.py */
#ifndef POUND_JIT_DECODER_ARM32_GENERATED_H
#define POUND_JIT_DECODER_ARM32_GENERATED_H

3
src/jit/interpreter/a32/instruction.c Normal file
View file

@ -0,0 +1,3 @@
/*
* Defines pvm_jit_interpreter_instruction_t struct and its internal opcodes.
*/

0
src/jit/interpreter/arm32/translator.c → src/jit/interpreter/a32/translator.c
View file

251
src/jit/interpreter/arm32/handler_table.inc
View file

@ -1,251 +0,0 @@
[PVM_A32_OP_DMB] = &&PVM_A32_OP_DMB,
[PVM_A32_OP_DSB] = &&PVM_A32_OP_DSB,
[PVM_A32_OP_ISB] = &&PVM_A32_OP_ISB,
[PVM_A32_OP_BLX_IMM] = &&PVM_A32_OP_BLX_IMM,
[PVM_A32_OP_BLX_REG] = &&PVM_A32_OP_BLX_REG,
[PVM_A32_OP_B] = &&PVM_A32_OP_B,
[PVM_A32_OP_BL] = &&PVM_A32_OP_BL,
[PVM_A32_OP_BX] = &&PVM_A32_OP_BX,
[PVM_A32_OP_BXJ] = &&PVM_A32_OP_BXJ,
[PVM_A32_OP_RFE] = &&PVM_A32_OP_RFE,
[PVM_A32_OP_SRS] = &&PVM_A32_OP_SRS,
[PVM_A32_OP_CPS] = &&PVM_A32_OP_CPS,
[PVM_A32_OP_SETEND] = &&PVM_A32_OP_SETEND,
[PVM_A32_OP_CRC32] = &&PVM_A32_OP_CRC32,
[PVM_A32_OP_CRC32C] = &&PVM_A32_OP_CRC32C,
[PVM_A32_OP_CDP] = &&PVM_A32_OP_CDP,
[PVM_A32_OP_MCR] = &&PVM_A32_OP_MCR,
[PVM_A32_OP_MCRR] = &&PVM_A32_OP_MCRR,
[PVM_A32_OP_MRC] = &&PVM_A32_OP_MRC,
[PVM_A32_OP_MRRC] = &&PVM_A32_OP_MRRC,
[PVM_A32_OP_LDC] = &&PVM_A32_OP_LDC,
[PVM_A32_OP_STC] = &&PVM_A32_OP_STC,
[PVM_A32_OP_ADC_IMM] = &&PVM_A32_OP_ADC_IMM,
[PVM_A32_OP_ADC_REG] = &&PVM_A32_OP_ADC_REG,
[PVM_A32_OP_ADC_RSR] = &&PVM_A32_OP_ADC_RSR,
[PVM_A32_OP_ADD_IMM] = &&PVM_A32_OP_ADD_IMM,
[PVM_A32_OP_ADD_REG] = &&PVM_A32_OP_ADD_REG,
[PVM_A32_OP_ADD_RSR] = &&PVM_A32_OP_ADD_RSR,
[PVM_A32_OP_AND_IMM] = &&PVM_A32_OP_AND_IMM,
[PVM_A32_OP_AND_REG] = &&PVM_A32_OP_AND_REG,
[PVM_A32_OP_AND_RSR] = &&PVM_A32_OP_AND_RSR,
[PVM_A32_OP_BIC_IMM] = &&PVM_A32_OP_BIC_IMM,
[PVM_A32_OP_BIC_REG] = &&PVM_A32_OP_BIC_REG,
[PVM_A32_OP_BIC_RSR] = &&PVM_A32_OP_BIC_RSR,
[PVM_A32_OP_CMN_IMM] = &&PVM_A32_OP_CMN_IMM,
[PVM_A32_OP_CMN_REG] = &&PVM_A32_OP_CMN_REG,
[PVM_A32_OP_CMN_RSR] = &&PVM_A32_OP_CMN_RSR,
[PVM_A32_OP_CMP_IMM] = &&PVM_A32_OP_CMP_IMM,
[PVM_A32_OP_CMP_REG] = &&PVM_A32_OP_CMP_REG,
[PVM_A32_OP_CMP_RSR] = &&PVM_A32_OP_CMP_RSR,
[PVM_A32_OP_EOR_IMM] = &&PVM_A32_OP_EOR_IMM,
[PVM_A32_OP_EOR_REG] = &&PVM_A32_OP_EOR_REG,
[PVM_A32_OP_EOR_RSR] = &&PVM_A32_OP_EOR_RSR,
[PVM_A32_OP_MOV_IMM] = &&PVM_A32_OP_MOV_IMM,
[PVM_A32_OP_MOV_REG] = &&PVM_A32_OP_MOV_REG,
[PVM_A32_OP_MOV_RSR] = &&PVM_A32_OP_MOV_RSR,
[PVM_A32_OP_MVN_IMM] = &&PVM_A32_OP_MVN_IMM,
[PVM_A32_OP_MVN_REG] = &&PVM_A32_OP_MVN_REG,
[PVM_A32_OP_MVN_RSR] = &&PVM_A32_OP_MVN_RSR,
[PVM_A32_OP_ORR_IMM] = &&PVM_A32_OP_ORR_IMM,
[PVM_A32_OP_ORR_REG] = &&PVM_A32_OP_ORR_REG,
[PVM_A32_OP_ORR_RSR] = &&PVM_A32_OP_ORR_RSR,
[PVM_A32_OP_RSB_IMM] = &&PVM_A32_OP_RSB_IMM,
[PVM_A32_OP_RSB_REG] = &&PVM_A32_OP_RSB_REG,
[PVM_A32_OP_RSB_RSR] = &&PVM_A32_OP_RSB_RSR,
[PVM_A32_OP_RSC_IMM] = &&PVM_A32_OP_RSC_IMM,
[PVM_A32_OP_RSC_REG] = &&PVM_A32_OP_RSC_REG,
[PVM_A32_OP_RSC_RSR] = &&PVM_A32_OP_RSC_RSR,
[PVM_A32_OP_SBC_IMM] = &&PVM_A32_OP_SBC_IMM,
[PVM_A32_OP_SBC_REG] = &&PVM_A32_OP_SBC_REG,
[PVM_A32_OP_SBC_RSR] = &&PVM_A32_OP_SBC_RSR,
[PVM_A32_OP_SUB_IMM] = &&PVM_A32_OP_SUB_IMM,
[PVM_A32_OP_SUB_REG] = &&PVM_A32_OP_SUB_REG,
[PVM_A32_OP_SUB_RSR] = &&PVM_A32_OP_SUB_RSR,
[PVM_A32_OP_TEQ_IMM] = &&PVM_A32_OP_TEQ_IMM,
[PVM_A32_OP_TEQ_REG] = &&PVM_A32_OP_TEQ_REG,
[PVM_A32_OP_TEQ_RSR] = &&PVM_A32_OP_TEQ_RSR,
[PVM_A32_OP_TST_IMM] = &&PVM_A32_OP_TST_IMM,
[PVM_A32_OP_TST_REG] = &&PVM_A32_OP_TST_REG,
[PVM_A32_OP_TST_RSR] = &&PVM_A32_OP_TST_RSR,
[PVM_A32_OP_BKPT] = &&PVM_A32_OP_BKPT,
[PVM_A32_OP_SVC] = &&PVM_A32_OP_SVC,
[PVM_A32_OP_UDF] = &&PVM_A32_OP_UDF,
[PVM_A32_OP_SXTB] = &&PVM_A32_OP_SXTB,
[PVM_A32_OP_SXTB16] = &&PVM_A32_OP_SXTB16,
[PVM_A32_OP_SXTH] = &&PVM_A32_OP_SXTH,
[PVM_A32_OP_SXTAB] = &&PVM_A32_OP_SXTAB,
[PVM_A32_OP_SXTAB16] = &&PVM_A32_OP_SXTAB16,
[PVM_A32_OP_SXTAH] = &&PVM_A32_OP_SXTAH,
[PVM_A32_OP_UXTB] = &&PVM_A32_OP_UXTB,
[PVM_A32_OP_UXTB16] = &&PVM_A32_OP_UXTB16,
[PVM_A32_OP_UXTH] = &&PVM_A32_OP_UXTH,
[PVM_A32_OP_UXTAB] = &&PVM_A32_OP_UXTAB,
[PVM_A32_OP_UXTAB16] = &&PVM_A32_OP_UXTAB16,
[PVM_A32_OP_UXTAH] = &&PVM_A32_OP_UXTAH,
[PVM_A32_OP_PLD_IMM] = &&PVM_A32_OP_PLD_IMM,
[PVM_A32_OP_PLD_REG] = &&PVM_A32_OP_PLD_REG,
[PVM_A32_OP_SEV] = &&PVM_A32_OP_SEV,
[PVM_A32_OP_SEVL] = &&PVM_A32_OP_SEVL,
[PVM_A32_OP_WFE] = &&PVM_A32_OP_WFE,
[PVM_A32_OP_WFI] = &&PVM_A32_OP_WFI,
[PVM_A32_OP_YIELD] = &&PVM_A32_OP_YIELD,
[PVM_A32_OP_NOP] = &&PVM_A32_OP_NOP,
[PVM_A32_OP_CLREX] = &&PVM_A32_OP_CLREX,
[PVM_A32_OP_SWP] = &&PVM_A32_OP_SWP,
[PVM_A32_OP_SWPB] = &&PVM_A32_OP_SWPB,
[PVM_A32_OP_STL] = &&PVM_A32_OP_STL,
[PVM_A32_OP_STLEX] = &&PVM_A32_OP_STLEX,
[PVM_A32_OP_STREX] = &&PVM_A32_OP_STREX,
[PVM_A32_OP_LDA] = &&PVM_A32_OP_LDA,
[PVM_A32_OP_LDAEX] = &&PVM_A32_OP_LDAEX,
[PVM_A32_OP_LDREX] = &&PVM_A32_OP_LDREX,
[PVM_A32_OP_STLEXD] = &&PVM_A32_OP_STLEXD,
[PVM_A32_OP_STREXD] = &&PVM_A32_OP_STREXD,
[PVM_A32_OP_LDAEXD] = &&PVM_A32_OP_LDAEXD,
[PVM_A32_OP_LDREXD] = &&PVM_A32_OP_LDREXD,
[PVM_A32_OP_STLB] = &&PVM_A32_OP_STLB,
[PVM_A32_OP_STLEXB] = &&PVM_A32_OP_STLEXB,
[PVM_A32_OP_STREXB] = &&PVM_A32_OP_STREXB,
[PVM_A32_OP_LDAB] = &&PVM_A32_OP_LDAB,
[PVM_A32_OP_LDAEXB] = &&PVM_A32_OP_LDAEXB,
[PVM_A32_OP_LDREXB] = &&PVM_A32_OP_LDREXB,
[PVM_A32_OP_STLH] = &&PVM_A32_OP_STLH,
[PVM_A32_OP_STLEXH] = &&PVM_A32_OP_STLEXH,
[PVM_A32_OP_STREXH] = &&PVM_A32_OP_STREXH,
[PVM_A32_OP_LDAH] = &&PVM_A32_OP_LDAH,
[PVM_A32_OP_LDAEXH] = &&PVM_A32_OP_LDAEXH,
[PVM_A32_OP_LDREXH] = &&PVM_A32_OP_LDREXH,
[PVM_A32_OP_LDRBT] = &&PVM_A32_OP_LDRBT,
[PVM_A32_OP_LDRHT] = &&PVM_A32_OP_LDRHT,
[PVM_A32_OP_LDRSBT] = &&PVM_A32_OP_LDRSBT,
[PVM_A32_OP_LDRSHT] = &&PVM_A32_OP_LDRSHT,
[PVM_A32_OP_LDRT] = &&PVM_A32_OP_LDRT,
[PVM_A32_OP_STRBT] = &&PVM_A32_OP_STRBT,
[PVM_A32_OP_STRHT] = &&PVM_A32_OP_STRHT,
[PVM_A32_OP_STRT] = &&PVM_A32_OP_STRT,
[PVM_A32_OP_LDR_LIT] = &&PVM_A32_OP_LDR_LIT,
[PVM_A32_OP_LDR_IMM] = &&PVM_A32_OP_LDR_IMM,
[PVM_A32_OP_LDR_REG] = &&PVM_A32_OP_LDR_REG,
[PVM_A32_OP_LDRB_LIT] = &&PVM_A32_OP_LDRB_LIT,
[PVM_A32_OP_LDRB_IMM] = &&PVM_A32_OP_LDRB_IMM,
[PVM_A32_OP_LDRB_REG] = &&PVM_A32_OP_LDRB_REG,
[PVM_A32_OP_LDRD_LIT] = &&PVM_A32_OP_LDRD_LIT,
[PVM_A32_OP_LDRD_IMM] = &&PVM_A32_OP_LDRD_IMM,
[PVM_A32_OP_LDRD_REG] = &&PVM_A32_OP_LDRD_REG,
[PVM_A32_OP_LDRH_LIT] = &&PVM_A32_OP_LDRH_LIT,
[PVM_A32_OP_LDRH_IMM] = &&PVM_A32_OP_LDRH_IMM,
[PVM_A32_OP_LDRH_REG] = &&PVM_A32_OP_LDRH_REG,
[PVM_A32_OP_LDRSB_LIT] = &&PVM_A32_OP_LDRSB_LIT,
[PVM_A32_OP_LDRSB_IMM] = &&PVM_A32_OP_LDRSB_IMM,
[PVM_A32_OP_LDRSB_REG] = &&PVM_A32_OP_LDRSB_REG,
[PVM_A32_OP_LDRSH_LIT] = &&PVM_A32_OP_LDRSH_LIT,
[PVM_A32_OP_LDRSH_IMM] = &&PVM_A32_OP_LDRSH_IMM,
[PVM_A32_OP_LDRSH_REG] = &&PVM_A32_OP_LDRSH_REG,
[PVM_A32_OP_STR_IMM] = &&PVM_A32_OP_STR_IMM,
[PVM_A32_OP_STR_REG] = &&PVM_A32_OP_STR_REG,
[PVM_A32_OP_STRB_IMM] = &&PVM_A32_OP_STRB_IMM,
[PVM_A32_OP_STRB_REG] = &&PVM_A32_OP_STRB_REG,
[PVM_A32_OP_STRD_IMM] = &&PVM_A32_OP_STRD_IMM,
[PVM_A32_OP_STRD_REG] = &&PVM_A32_OP_STRD_REG,
[PVM_A32_OP_STRH_IMM] = &&PVM_A32_OP_STRH_IMM,
[PVM_A32_OP_STRH_REG] = &&PVM_A32_OP_STRH_REG,
[PVM_A32_OP_LDM] = &&PVM_A32_OP_LDM,
[PVM_A32_OP_LDMDA] = &&PVM_A32_OP_LDMDA,
[PVM_A32_OP_LDMDB] = &&PVM_A32_OP_LDMDB,
[PVM_A32_OP_LDMIB] = &&PVM_A32_OP_LDMIB,
[PVM_A32_OP_LDM_USR] = &&PVM_A32_OP_LDM_USR,
[PVM_A32_OP_LDM_ERET] = &&PVM_A32_OP_LDM_ERET,
[PVM_A32_OP_STM] = &&PVM_A32_OP_STM,
[PVM_A32_OP_STMDA] = &&PVM_A32_OP_STMDA,
[PVM_A32_OP_STMDB] = &&PVM_A32_OP_STMDB,
[PVM_A32_OP_STMIB] = &&PVM_A32_OP_STMIB,
[PVM_A32_OP_STM_USR] = &&PVM_A32_OP_STM_USR,
[PVM_A32_OP_BFC] = &&PVM_A32_OP_BFC,
[PVM_A32_OP_BFI] = &&PVM_A32_OP_BFI,
[PVM_A32_OP_CLZ] = &&PVM_A32_OP_CLZ,
[PVM_A32_OP_MOVT] = &&PVM_A32_OP_MOVT,
[PVM_A32_OP_MOVW] = &&PVM_A32_OP_MOVW,
[PVM_A32_OP_SBFX] = &&PVM_A32_OP_SBFX,
[PVM_A32_OP_SEL] = &&PVM_A32_OP_SEL,
[PVM_A32_OP_UBFX] = &&PVM_A32_OP_UBFX,
[PVM_A32_OP_USAD8] = &&PVM_A32_OP_USAD8,
[PVM_A32_OP_USADA8] = &&PVM_A32_OP_USADA8,
[PVM_A32_OP_PKHBT] = &&PVM_A32_OP_PKHBT,
[PVM_A32_OP_PKHTB] = &&PVM_A32_OP_PKHTB,
[PVM_A32_OP_RBIT] = &&PVM_A32_OP_RBIT,
[PVM_A32_OP_REV] = &&PVM_A32_OP_REV,
[PVM_A32_OP_REV16] = &&PVM_A32_OP_REV16,
[PVM_A32_OP_REVSH] = &&PVM_A32_OP_REVSH,
[PVM_A32_OP_SSAT] = &&PVM_A32_OP_SSAT,
[PVM_A32_OP_SSAT16] = &&PVM_A32_OP_SSAT16,
[PVM_A32_OP_USAT] = &&PVM_A32_OP_USAT,
[PVM_A32_OP_USAT16] = &&PVM_A32_OP_USAT16,
[PVM_A32_OP_SDIV] = &&PVM_A32_OP_SDIV,
[PVM_A32_OP_UDIV] = &&PVM_A32_OP_UDIV,
[PVM_A32_OP_MLA] = &&PVM_A32_OP_MLA,
[PVM_A32_OP_MLS] = &&PVM_A32_OP_MLS,
[PVM_A32_OP_MUL] = &&PVM_A32_OP_MUL,
[PVM_A32_OP_SMLAL] = &&PVM_A32_OP_SMLAL,
[PVM_A32_OP_SMULL] = &&PVM_A32_OP_SMULL,
[PVM_A32_OP_UMAAL] = &&PVM_A32_OP_UMAAL,
[PVM_A32_OP_UMLAL] = &&PVM_A32_OP_UMLAL,
[PVM_A32_OP_UMULL] = &&PVM_A32_OP_UMULL,
[PVM_A32_OP_SMLALXY] = &&PVM_A32_OP_SMLALXY,
[PVM_A32_OP_SMLAXY] = &&PVM_A32_OP_SMLAXY,
[PVM_A32_OP_SMULXY] = &&PVM_A32_OP_SMULXY,
[PVM_A32_OP_SMLAWY] = &&PVM_A32_OP_SMLAWY,
[PVM_A32_OP_SMULWY] = &&PVM_A32_OP_SMULWY,
[PVM_A32_OP_SMMUL] = &&PVM_A32_OP_SMMUL,
[PVM_A32_OP_SMMLA] = &&PVM_A32_OP_SMMLA,
[PVM_A32_OP_SMMLS] = &&PVM_A32_OP_SMMLS,
[PVM_A32_OP_SMUAD] = &&PVM_A32_OP_SMUAD,
[PVM_A32_OP_SMLAD] = &&PVM_A32_OP_SMLAD,
[PVM_A32_OP_SMLALD] = &&PVM_A32_OP_SMLALD,
[PVM_A32_OP_SMUSD] = &&PVM_A32_OP_SMUSD,
[PVM_A32_OP_SMLSD] = &&PVM_A32_OP_SMLSD,
[PVM_A32_OP_SMLSLD] = &&PVM_A32_OP_SMLSLD,
[PVM_A32_OP_SADD8] = &&PVM_A32_OP_SADD8,
[PVM_A32_OP_SADD16] = &&PVM_A32_OP_SADD16,
[PVM_A32_OP_SASX] = &&PVM_A32_OP_SASX,
[PVM_A32_OP_SSAX] = &&PVM_A32_OP_SSAX,
[PVM_A32_OP_SSUB8] = &&PVM_A32_OP_SSUB8,
[PVM_A32_OP_SSUB16] = &&PVM_A32_OP_SSUB16,
[PVM_A32_OP_UADD8] = &&PVM_A32_OP_UADD8,
[PVM_A32_OP_UADD16] = &&PVM_A32_OP_UADD16,
[PVM_A32_OP_UASX] = &&PVM_A32_OP_UASX,
[PVM_A32_OP_USAX] = &&PVM_A32_OP_USAX,
[PVM_A32_OP_USUB8] = &&PVM_A32_OP_USUB8,
[PVM_A32_OP_USUB16] = &&PVM_A32_OP_USUB16,
[PVM_A32_OP_QADD8] = &&PVM_A32_OP_QADD8,
[PVM_A32_OP_QADD16] = &&PVM_A32_OP_QADD16,
[PVM_A32_OP_QASX] = &&PVM_A32_OP_QASX,
[PVM_A32_OP_QSAX] = &&PVM_A32_OP_QSAX,
[PVM_A32_OP_QSUB8] = &&PVM_A32_OP_QSUB8,
[PVM_A32_OP_QSUB16] = &&PVM_A32_OP_QSUB16,
[PVM_A32_OP_UQADD8] = &&PVM_A32_OP_UQADD8,
[PVM_A32_OP_UQADD16] = &&PVM_A32_OP_UQADD16,
[PVM_A32_OP_UQASX] = &&PVM_A32_OP_UQASX,
[PVM_A32_OP_UQSAX] = &&PVM_A32_OP_UQSAX,
[PVM_A32_OP_UQSUB8] = &&PVM_A32_OP_UQSUB8,
[PVM_A32_OP_UQSUB16] = &&PVM_A32_OP_UQSUB16,
[PVM_A32_OP_SHADD8] = &&PVM_A32_OP_SHADD8,
[PVM_A32_OP_SHADD16] = &&PVM_A32_OP_SHADD16,
[PVM_A32_OP_SHASX] = &&PVM_A32_OP_SHASX,
[PVM_A32_OP_SHSAX] = &&PVM_A32_OP_SHSAX,
[PVM_A32_OP_SHSUB8] = &&PVM_A32_OP_SHSUB8,
[PVM_A32_OP_SHSUB16] = &&PVM_A32_OP_SHSUB16,
[PVM_A32_OP_UHADD8] = &&PVM_A32_OP_UHADD8,
[PVM_A32_OP_UHADD16] = &&PVM_A32_OP_UHADD16,
[PVM_A32_OP_UHASX] = &&PVM_A32_OP_UHASX,
[PVM_A32_OP_UHSAX] = &&PVM_A32_OP_UHSAX,
[PVM_A32_OP_UHSUB8] = &&PVM_A32_OP_UHSUB8,
[PVM_A32_OP_UHSUB16] = &&PVM_A32_OP_UHSUB16,
[PVM_A32_OP_QADD] = &&PVM_A32_OP_QADD,
[PVM_A32_OP_QSUB] = &&PVM_A32_OP_QSUB,
[PVM_A32_OP_QDADD] = &&PVM_A32_OP_QDADD,
[PVM_A32_OP_QDSUB] = &&PVM_A32_OP_QDSUB,
[PVM_A32_OP_MRS] = &&PVM_A32_OP_MRS,
[PVM_A32_OP_MSR_IMM] = &&PVM_A32_OP_MSR_IMM,
[PVM_A32_OP_MSR_REG] = &&PVM_A32_OP_MSR_REG,
[PVM_A32_OP_STOP] = &&PVM_A32_OP_STOP,

1255
src/jit/interpreter/arm32/handlers.inc
View file

File diff suppressed because it is too large Load diff

1261
src/jit/interpreter/arm32/handlers.inc.skeleton
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File diff suppressed because it is too large Load diff

101
src/jit/interpreter/arm32/instruction.c
View file

@ -1,101 +0,0 @@
/*
* Defines pvm_jit_interpreter_arm32_instruction_t struct and its internal
* opcodes.
*/
#include "frontend/decoder/arm32_opcodes.h"
#include "common/passert.h"
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
/*
* Computed gotos are a GCC/Clang extension that significantly improves
* interpreter performance by predicting branch targets.
*/
#if defined(__GNUC__) || defined(__clang__)
#define PVM_USE_COMPUTED_GOTO 1
#else
#define PVM_USE_COMPUTED_GOTO 0
#endif
typedef struct
{
uint32_t GPRs[16];
uint32_t PSTATE;
} pvm_jit_interpreter_arm32_cpu_state_t;
typedef struct
{
pvm_jit_decoder_arm32_opcode_t opcode;
} pvm_jit_interpreter_arm32_instruction_t;
void
temp (void)
{
pvm_jit_interpreter_arm32_instruction_t *instr = calloc(3, sizeof(*instr));
instr->opcode = PVM_A32_OP_ADD_REG;
(++instr)->opcode = PVM_A32_OP_STOP;
/*
* Uses a jump table with address labels (&&LABEL) to dispatch directly to the
* handler.
*/
#if PVM_USE_COMPUTED_GOTO
/* The dispatch table contains the address of every label in handlers.inc */
static const void *const dispatch_table[] = {
#include "handler_table.inc"
};
/*
* HANDLER macro defines the label target.
* DISPATCH macro increments IP and jumps to the next handler.
*/
#define HANDLER(name) name
#define DISPATCH() \
do \
{ \
instr++; \
goto *dispatch_table[instr->opcode]; \
} while (0)
/* Must perform the initial jump to start the race. */
goto *dispatch_table[instr->opcode];
/* Include the instruction logic */
#include "handlers.inc"
#undef HANDLER
#undef DISPATCH
/*
* Uses a standard switch statement. Slower due to bounds checking and lack of
* branch prediction, but 100% portable and safe.
*/
#else
/*
* HANDLER macro defines a switch case.
* DISPATCH macro jumps back to the switch statement.
*/
#define HANDLER(name) case name
#define DISPATCH() goto dispatch_loop
dispatch_loop:
switch (instr->opcode)
{
/* Include the instruction logic */
#include "handlers.inc"
default:
PVM_ASSERT_MSG(
0, "Invalid Opcode in interpreter dispatch: %d", instr->opcode);
break;
}
#undef HANDLER
#undef DISPATCH
#endif
}

1
src/jit/interpreter/arm32/instruction.h
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@ -1 +0,0 @@
void temp(void);

2
tests/jit/decoder/test_arm32_generated.cpp
View file

@ -1,7 +1,7 @@
/*
* GENERATED FILE - DO NOT EDIT
*
* This file is generated by scripts/generate_jit_decoder_tests.py
* This file is generated by scripts/generate_decoder_tests.py
*
* PURPOSE:
* Provides 100% requirements-based test coverage for the ARM32 Instruction Decoder.